Silicon Investor (SI) -- The First Internet Community

STOCKTALK

We've detected that you're using an ad content blocking browser plug-in or feature. Ads provide a critical source of revenue to the continued operation of Silicon Investor. We ask that you disable ad blocking while on Silicon Investor in the best interests of our community. If you are not using an ad blocker but are still receiving this message, make sure your browser's tracking protection is set to the 'standard' level.

Politics : Formerly About Advanced Micro Devices -- Ignore unavailable to you. Want to Upgrade?

To: Scumbria who wrote (114172)	6/4/2000 10:38:00 PM
From: wily	Respond to of 1576322

Scumbria, A lot. Probably 10-100% performance improvement, depending on the benchmark. Wow! Thanks. wily

To: Scumbria who wrote (114172)	6/4/2000 10:52:00 PM
From: wily	Read Replies (1) \| Respond to of 1576322

Scumbria, Another performance boost will come from increasing the frequency of the secondary cache. The integrated cache runs at the same speed as the processor core. The off-die Athlon cache was originally intended to run at half the speed of the processor. But Bode said off-die cache speeds have reached a ceiling in the mid-300-MHz range. Chips with processor cores exceeding 700 MHz have suffered a performance hit because the L2 cache runs at less than half the speed of the processor core. McCarron said one recently produced 1-GHz Athlon featured a 350-MHz cache-just a bit better than one-third the speed of the core. Message 13825731 What limits the speed to 350MHz in this instance (i.e., off-die L2 SRAM caches)? wily

To: Scumbria who wrote (114172)	6/4/2000 10:54:00 PM
From: Trent George	Read Replies (1) \| Respond to of 1576322

There are conflicting specifications for the TBird. Tom says 112mm^2 up to 1.2GHz and 256bit width L2 Cache bus Anandtech says 120mm^2 to 1Ghz and 64bit width L2 Cache. I think they are both guessing ! I think 16 way L2 cache would suggest a smaller L2 cache line (64 bit seems appropriate) 64bit would also be more in line with 64bit sdram and should reduce latency on a cache line fill from RAM, also with exclusive cache (L1 & L2) there will never be a ram to L2 fill but only a L1 > L2 and RAM > L1, right ? 64 bits would make everything go in the same cycle? vs 256 Coppermine does 4 sets of 64 bits into L2 and L1 from SDRAM, delaying things until all 256 bits are in, but speeding things for access to subsequent (now in cache) access? Any comments from anyone ?