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Politics : Formerly About Advanced Micro Devices -- Ignore unavailable to you. Want to Upgrade?

To: Tenchusatsu who wrote (114260)	6/5/2000 2:20:00 AM
From: Cirruslvr	Read Replies (1) \| Respond to of 1575617

Tench - RE: "The 64-bit BSB width is surprising to me. With the "exclusive" L2 cache (a.k.a. Victim Cache), I figure T-bird will need the BSB bandwidth a LOT more than Coppermine because of all the swapping of data between L1 and L2. Maybe AMD will increase the BSB width on Mustang." This means Cumine's L2 cache has double the bandwidth, right? Athlon has 64bit BSB that I assume works at full speed while Cumine has 256bit, but is half speed (or sends every other clock). It would seem to a technically illiterate person like me that since the Athlon has 4X the L1 cache of Cumine, it would need more L2 bandwidth to send the send data. Does that make sense? Whatever the AMD engineers' reasoning to do what they did was, I am sure it made sense. They DID design the Athlon... Does having a wider BSB width have any effect on limiting on clock speed? Maybe AMD engineers didn't want to risk it. Are you more confident about Willy now?

To: Tenchusatsu who wrote (114260)	6/5/2000 2:23:00 AM
From: Scumbria	Read Replies (1) \| Respond to of 1575617

Ten, 1) T-bird has a higher L2 associativity (16-way) than Coppermine (8-way). The benefit of this is slightly fewer L2 cache misses. The trade-off here, however, is the longer latency: a higher associativity slows down the cache. That's why the longer latency is required. There is no reason why higher associativity should slow down an onboard L2 cache. Tag comparison can begin as soon as the TLB lookup is completed. Data array access is independent of associativity. The mux logic out can be set up immediately after tag comparison is completed. 2) The 64-bit BSB width is surprising to me. With the "exclusive" L2 cache (a.k.a. Victim Cache), I figure T-bird will need the BSB bandwidth a LOT more than Coppermine because of all the swapping of data between L1 and L2. Maybe AMD will increase the BSB width on Mustang. BSB is an Intel term. There will be much less swapping between the T-Bird caches, than between the PIII caches. This is because the PIII L1 is only 1/4 the size of the T-Bird L1, and has a much higher miss rate. T-Bird does not need as much bandwidth between caches, as PIII. The only really important beat of data is the first one, and a 64 bit bus is more than adequate to fill that need. Scumbria

To: Tenchusatsu who wrote (114260)	6/5/2000 2:27:00 AM
From: Charles R	Respond to of 1575617

Tenchusatsu, <Two comments: 1) T-bird has a higher L2 associativity (16-way) than Coppermine (8-way). The benefit of this is slightly fewer L2 cache misses. The trade-off here, however, is the longer latency: a higher associativity slows down the cache. That's why the longer latency is required. 2) The 64-bit BSB width is surprising to me. With the "exclusive" L2 cache (a.k.a. Victim Cache), I figure T-bird will need the BSB bandwidth a LOT more than Coppermine because of all the swapping of data between L1 and L2. Maybe AMD will increase the BSB width on Mustang.> The first order effects here are latency and exclusivity (in that order). Thunderbird loses to PIII on the first and gains on the second. Given the tiny amount of misses that actually go from L1 to L2, it is hard for me to even think that the 64-bit data path is a problem (assuming critical-word first read). What do you think Scumbria? Edit: I just looked at your response to Tench - looks like we agree. Chuck