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Politics : Formerly About Advanced Micro Devices -- Ignore unavailable to you. Want to Upgrade?

To: Cirruslvr who wrote (114269)	6/5/2000 2:51:00 AM
From: Tenchusatsu	Respond to of 1575623

Cirrus, <This means Cumine's L2 cache has double the bandwidth, right? Athlon has 64bit BSB that I assume works at full speed while Cumine has 256bit, but is half speed (or sends every other clock).> Perhaps. If T-bird BSB has a single bi-directional data path, then the bandwidth would be even worse. However, I'll assume the best, that T-bird has two uni-directional data paths, just like Coppermine. <It would seem to a technically illiterate person like me that since the Athlon has 4X the L1 cache of Cumine, it would need more L2 bandwidth to send the send data. Does that make sense?> Not really. If anything, a larger L1 cache would mean less reliance on L2, meaning less BSB bandwidth. <Does having a wider BSB width have any effect on limiting on clock speed?> I doubt it. I really don't know why the AMD engineers didn't widen the BSB. Maybe AMD didn't want to risk it. Perhaps they ran performance simulations which showed a wider BSB wouldn't make much of a difference. Maybe AMD is saving it for Mustang. <Are you more confident about Willy now?> Actually, my fear isn't whether AMD will have any answer to Willamette. My fear is more universal, that hardware has gone sooooooooooo far ahead of software that by the time Willamette gets going, performance really won't matter anymore, except for the low-volume markets. Tenchusatsu