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Politics : Formerly About Advanced Micro Devices -- Ignore unavailable to you. Want to Upgrade?

To: steve harris who wrote (114681)	6/6/2000 7:41:00 PM
From: Joe NYC	Read Replies (1) \| Respond to of 1573050

Interview with AMD's Drew Prairie (thanks to Gene Parrott of the RMBS thread): Q:What is the L2 latency of Thunderbird? For Thunderbird, is the L2 request sent simultaneously with the L1 request, or is it only sent after an L1 miss is detected? What is the L2 bus width for Thunderbird? What is the L2 associativity of Thunderbird? A:We designed the large 128Kb L1 cache to deliver optimal processor performance by ensuring that the majority of performance-intensive memory requests are serviced by accessing the L1. the 128Kb L1 is 2-way set associative, and the L2 cache is 256Kb 16 way set associative. we use an exclusive cache architecture that delivers 384kb of effective cache memory on the CPU. Exclusive cache architecture contains only the copy-back cache blocks to be written back to the memory sub-system, so there is no redundancy between the L1 and L2. Because of the exclusive cache architecture, the L2 adds a full 256Kb of additional cache memory --- for the 384kb total of effective cache. The L2 has a 64-bit data path with an 8 cycle latency between an L1 miss and the first critical word received from the L2. what does it all mean in terms of overall CPU/system performance? Check the AMD website for a comprehensive set of benchmark results that demonstrate the benefits of our architecture in terms of delivering leading-edge performance. fullon3d.com Joe