Silicon Investor (SI) -- The First Internet Community

STOCKTALK

We've detected that you're using an ad content blocking browser plug-in or feature. Ads provide a critical source of revenue to the continued operation of Silicon Investor. We ask that you disable ad blocking while on Silicon Investor in the best interests of our community. If you are not using an ad blocker but are still receiving this message, make sure your browser's tracking protection is set to the 'standard' level.

Politics : Formerly About Advanced Micro Devices -- Ignore unavailable to you. Want to Upgrade?

To: Gopher Broke who wrote (114782)	6/7/2000 9:23:00 AM
From: Scumbria	Read Replies (1) \| Respond to of 1573211

Gopher, Surely this means that it is constraining overall clock speed because of the limitations on transistor switching speeds in those double clocked stages? All things other things being equal, could you not produce a faster Willy without the double clocked stages? It depends on the amount of logic in those double clocked stages. If the number of gates is very small, the double clocked ALU may not be the critical path of the chip. On the other hand, it is entirely possible that the ALU is the critical path, in which case the double clocking was a very dumb idea. There has been ambiguous information out of Intel about the number of clocks per ALU operation. If they really are trying to do a 32 bit add at 3GHz in one cycle (from Wu's presentation), I doubt they will ever get to 1.5 GHz in 0.18u. Scumbria