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To: Elmer who wrote (104150)	6/7/2000 6:48:00 PM
From: John Walliker	Respond to of 186894

Elmer, The RMBS bus itself uses differential pairs but that's only 16 bits plus the clocks ... Only the clock (forward and return) is fully differential. All the other RSL signals share a single reference line. John

To: Elmer who wrote (104150)	6/7/2000 7:05:00 PM
From: pgerassi	Read Replies (1) \| Respond to of 186894

Dear Elmer: RMBS uses 16 pins for data, 8 for address, 5 for control, plus power, clocks, etc. That is a total of 29 pins. The thing is that the modules need both an in set and an out set (serially connected). That makes 58 pins plus power. SDRAM modules have 72 pins for data (64 data and 8 ECC), 15 for address, and 8 for control, plus power, clocks, etc. That is 58 for RMBS and 95 for SDRAM. The controller needs one set only except for clocks. Thus a RMBS controller needs only 33 pins to 97 for SDRAM controller. That is about 1/3 as many for controllers and 2/3 for modules. However RMBS uses the same number of pins in a module as DDRSDRAM as each data, address, control, and clock line needs a ground pair for crosstalk control. However the tradeoff is a much tighter control required of RMBS pins due to the 3-4 times higher frequency. This makes RMBS pins more costly per pin (overall) than SDRAM or DDRSDRAM pins. Since chipsets are done with larger processes due to the smaller logic required against pin count, this tripling of pin count does not affect the chipset size. It still has to connect to the FSB, AGP, PCI busses. Those take up about 200 for FSB (Intel), 200 for AGP, 200 for PCI, and some miscellaneous. That is a starting point of around 600 pins. A 60 pin difference for one channel or 120 pin difference for dual channels does not make the northbridge chipset much bigger. 676 pins with bga is about 25 by 25 and 784 pins is about 28 by 28. This is not a whole lot larger for a dual channel DDR compared to a dual channel RMBS. To get the same bandwidth as PC2100 (133Mhz DDR), RMBS would have to be PC1066 (533Mhz DDR). Most of the problem with RMBS centers on how to make sure all the control and data signals stay synchronized with each other. This leads to the tight control. A serial connection does not have this issue as the data can be self clocking. To get the same bandwidth as PC1600 DDRSDRAM or PC800 DRDRAM, the serial bit rate would have to be about 16Ghz or so (64 bytes per transaction, 32 bits of address, plus ECC, synchronization, and/or CRCs). Latency would be about 40nsec plus comm delays (about 1nsec per 5" of trace length (out and back)). This leads to the same 2 pair or 4 pair at 8Ghz as ethernet. This would be the logical extension of RMBS. Modules would have only 8 pins, 2 pins xmit in, 2 pins recv in, 2 pins xmit out, and 2 pins recv out. Power is supplied by a DC bias between the xmit and recv pins. Thus RJ45 connectors or something similar could be used. Pete