Silicon Investor (SI) -- The First Internet Community

STOCKTALK

We've detected that you're using an ad content blocking browser plug-in or feature. Ads provide a critical source of revenue to the continued operation of Silicon Investor. We ask that you disable ad blocking while on Silicon Investor in the best interests of our community. If you are not using an ad blocker but are still receiving this message, make sure your browser's tracking protection is set to the 'standard' level.

Politics : Formerly About Advanced Micro Devices -- Ignore unavailable to you. Want to Upgrade?

To: wily who wrote (114911)	6/7/2000 10:45:00 PM
From: Joe NYC	Respond to of 1577984

Wily, What would be lost with a larger, slower on-chip cache vs a smaller, faster on-chip cache? For the comparison, suppose that the slower cache was 10X bigger or more. From performance point of view, there is no definite answer. It depends on application. If the part of the code that is critical to performance fits inside on-chip L2, the performance would be much better with on-chip cache. If the code doesn't fit inside on-chip cache, you may get a better performance from off chip cache. But even though the on-chip cache consumes die area, it is usually less expensive than cartridges of Slot 1 or Slot A CPUs. Joe

To: wily who wrote (114911)	6/8/2000 9:11:00 AM
From: Scumbria	Read Replies (1) \| Respond to of 1577984

Wily, What would be lost with a larger, slower on-chip cache vs a smaller, faster on-chip cache? For the comparison, suppose that the slower cache was 10X bigger or more. It depends on the application. If it fits in the smaller cache, it will get better performance with that cache. An application with a much larger working set can potentially get better performance with the larger cache. The 256K T-Bird cache can probably be made to run at 2X it's current speed. Scumbria