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Politics : Formerly About Advanced Micro Devices -- Ignore unavailable to you. Want to Upgrade?

To: Pravin Kamdar who wrote (114986)	6/9/2000 10:56:00 AM
From: pgerassi	Read Replies (2) \| Respond to of 1571782

Dear Pravin: Assuming that you mean from 200 DDR on PC133 to 266 DDR on PC2100. Since most applications are memory constrained and these assumptions show a doubling of available bandwidth, I would figure about a 5% to 15% increase overall. A high memory use program such as MPEG encoding or simulations would show a 25% to 50% improvement (latency cuts into effective rates, on PC133 its about 400 to 500 MB/sec and on PC2100 it would be about 700 to 900MB/sec). The 64 byte cache fill on Athlon is an advantage to the 32 byte cache fill on PIII when considering effective bandwidth of a technology. The effective rate is theoretical rate times data cycles divided by the sum of latency cycles plus data cycles. Thus decreasing latency helps both but more for PIII. Increasing the amount of data cycles makes sense, if the usage of the extra data is high. From most typical real world applications this appears to be true. It is said that in the early 90's, Intel did a study on current applications and determined that a cache line size of 32 bytes was most effective. The next most effective size was 64 bytes. It appears that Windows, Unix, and application code bloat has increased the size of routines above this breakpoint. Now the most effective size is 64 bytes and still trending up. Soon it will be 128 bytes. It is this trend that will ultimately help memory providers by changing the bandwidth versus latency tradeoffs. In addition, multi-tasking further allows more than one transfer to be in play at the same time. This will allow pipelining to become effective for the memory subsystem in PCs. I think RMBS is too early. Its main disadvantage can be traced to the small amount of memory in any given DRAM chip. At 64 or 128M bit chips, too many are needed for PCs for the concept to work. With current desired sizes, 128MB to 256MB (code bloat strikes again), 8 to 32 chips are far above the break even point. One or two chips is where the break even point is and that means 1 to 4G bits per chip are needed to make the concept work right. The additional circuitry would go from 30% of a 64M bit to 2% or 3% of a gigabit chip. Unfortunately for RMBS, PCs seem to stay at 8 to 16 chips of memory per PC and 256 to 1024 chips per server for the last 5 or 6 years. Their patents may expire before one or two chips are the norm. At that time embedded memory will be on the heels and stop it 2 to 5 years later (if that much). It is not looking good for RMBS. Pete