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Technology Stocks : Intel Corporation (INTC) -- Ignore unavailable to you. Want to Upgrade?

To: Tenchusatsu who wrote (104268)	6/9/2000 1:09:00 AM
From: Bilow	Read Replies (1) \| Respond to of 186894

Hi Tenchusatsu; Thanks for reading my references. By the way, I forgot to put the link to the i810 document, but I suppose you found it easily. Of course the number of signals that one has to route isn't a manufacturing consideration. But the board area required for those routes is, and that is what I made some effort to calculate. I think that you're right, and the i820 motherboards are, by and large, routed in four layers. The interesting detail about this is that the RSL signals have to routed over ground planes on either the top or bottom layers of the board. That means that in the region of the RSL signals, there is no VCC (maybe they call it VDD nowadays) plane. I'd be curious as to whether Dell used that technique. Naturally, Intel doesn't have a DDR design rules manual, but the industry word is that the widths are the same. So a 4-layer board should be the standard. In addition, the impedance requirements are much simpler, so the DDR boards are cheaper to design, build and test. It is highly unlikely that single channel DDR will require 6-layer boards. If 6 layers are required (which I'm pretty sure won't happen), it will be because of "escape" requirements at the memory controller chip, not because of trace widths. The number of layers required for escape is a more complicated subject than channel widths, but if you do a search on the IBM website, you can find some documents that give insight into the restrictions. Escape requirements are largely a function of pin count and density. By the way, I believe that it is only in the reduced pin count for the controller chip (and the possible reduction in board layer count) that RDRAM provides a motherboard advantage over DDR. The more pins required, the more likely that extra layers are required. The bigger the chip area of the controller, the fewer escape layers required. For this reason, a lot of manufacturers are backing away from the uBGA to a wider spaced BGA package, even though the BGA package is bigger and more expensive. Another issue is "blind" PCB vias, which are more expensive, but which tend to reduce the number of layers required to escape. In other words, just like with everything else in engineering, it is a complicated trade off, and there is not an easy answer. But I'll look around to see what the DDR people are saying about board layer requirements for the controller. It is true that the DDR DIMMs have a reference design that uses fewer board layers than RDRAM RIMMs: (See #reply-13485509, for complete notes and links. The industry reference PC100, PC133, and DDR DIMM designs use 6 layers, while the reference RIMM design is 8 layers.), but it is possible that this situation will be reversed in the motherboards. There are apparently 17 DDR chipsets under development, I doubt that all 17 will require more than 4 layers. I recognize that the fact that you work at Intel (still?) might constrain what you can say about their technology. Thanks again for taking the risk to respond. -- Carl P.S. I didn't mean to make a leap of logic to go from "RDRAM is physically wider than SDRAM" to "RDRAM is the worst technology ever to hit memory." If the issue of the channel routing on the motherboard was the only issue Rambus faced, we (including myself) would be agreed that it was the natural new technology. As you well know, RDRAM has a huge number of issues, far more than could be reasonably covered in several dozen posts.