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To: Bilow who wrote (43826)6/9/2000 10:04:00 AM
From: gnuman  Respond to of 93625
 
820E Design guide.
The new guide is out. (Very large .pdf file).
ftp://download.intel.com/design/chipsets/designex/29818701.pdf
A couple of comments. Can use a four layer mobo if micro strip line used vs strip line. Dielectric reduced from 7 to 4.5 mils. Sampling window, ("eye"), 1.25ns in clean system, with total allowable channel timing error of only 100ps. (Probably why there are still only two RIMM's). Detailed discussion on trace lengths, widths, isolation, routing, stack ups and via's. A very comprehensive document for those interested in the technology.
JMHO's