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To: pgerassi who wrote (104344)6/12/2000 12:38:00 AM
From: Elmer  Read Replies (1) | Respond to of 186894
 
Pete, you are correct in saying that the Athlon FSP(port) would not be shared in a dual Athlon system but the bottleneck is simply moved from the FSB, as with P6 based systems, to the memory controller. You haven't eliminated a bottleneck, only moved it to another location. In addition you have added additional latency and complexity when doing snoop cycles which the P6 system would not suffer. Seeing as nobody has ever seen a dual Athlon system I think we should wait for a real system, assuming one will eventually show up, before we jump to conclusions.

EP



To: pgerassi who wrote (104344)6/12/2000 1:32:00 AM
From: jim kelley  Read Replies (1) | Respond to of 186894
 
The QMC program is not representative of most PC applications. It is a specialized set of matrix operations and other calculations which have not been set up to run optimally on a RDRAM PC.


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