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Politics : Formerly About Advanced Micro Devices -- Ignore unavailable to you. Want to Upgrade?

To: pgerassi who wrote (115644)	6/12/2000 8:21:00 PM
From: Scumbria	Read Replies (2) \| Respond to of 1575949

Pete, The problem with the higher latency scores are due to the use of exclusive cache. The upside is that you are not duplicating the contents but, the downside is you have to write back the L1 cache victims. I saw your description of the T-Bird L2 read/write cycle, and it is not clear to me why the L2 is written to in the middle of an L2 read cycle. Shouldn't there be a large linefill buffer in the L2 to hold several lines, and write them back during periods of low L2 read activity? Frankly, it would make more sense to throw away overflowed linefill buffer accesses, than to put extra latency into every single L2 access. The L2 on T-Bird should only be used for about 1% of memory accesses. I don't see why an L2 linefill coming from the L1 needs to be any more expensive than an L2 linefill coming from DRAM (in an inclusive cache.) Hope I'm not offending anyone, but I think the T-Bird L2 is a dog. Scumbria