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To: Estephen who wrote (44841)	6/17/2000 6:54:00 PM
From: Estephen	Read Replies (1) \| Respond to of 93625

6/16/00 - Panelists look to future needs of embedded design Jun. 16, 2000 (Electronic Engineering Times - CMP via COMTEX) -- LOS ANGELES - Design reuse and use of third-party digital and analog IP are imperative for today's bleeding-edge IC design flows but a lack of quality engineers, high capacity verification solutions and "IP aware" tools are hampering design efforts. That was the message delivered here at a Design Automation Conference panel titled "Embedded Systems Design in the New Millennium." In the panel, moderated by UC Berkeley Professor Richard Newton, ARM chief technologist Tudor Brown said that while opportunities in the electronics industry are growing, the shortage of quality engineers is making reuse imperative for companies to get products out the door. The winners in electronics are going to be those companies that "get designs done quickest with the least amount of effort." "The optimal solution doesn't actually mean a perfect solution. It actually means a solution that exists and does what is needed," Brown said. "Many of the most successful solutions today come from compromises." Brown said the trick to becoming a winner in design is knowing how and when to compromise. "It is very tempting to add on features to a design, but every feature adds time and cost, he said. "It may not cost money maybe but it costs you documentation time, testing time and programming time." Configurable IP, for example, allows users to easily add new features to a design but causes slowdowns downstream in test and documentation, Brown said. Rambus chief executive Geoff Tate said engineers need to consider whether putting all these complexities on a single chip is better than using serveral chips and deciding whether it is better to design vs. license. To get the most of licensing, companies have to structure a license so that the IP vendor only makes money if your company makes money, he added. Wally Rhines, president and chief executive of Mentor Graphics, said the majority of EDA tools used today for design capture, debug simulate and verify designs "are not insightful or IP-aware enough for the era ahead." Companies are failing to supply tools that allow customers to properly document cores for end users-causing great problems downstream, he said. Future tools will be able to intelligently instantiate cores instead of making users look at electrical signal models, Rhines notes. "You want to be able to look at a project as not a bundle of electrical signals but at a semantic level with rules associated with how those wire have to be hooked up," he said. Signal-processor debug tools, he said, are also going to have to change and not look just at the interconnect between cores but take into account the specific IP being used and the RTOS that is embedded in the system. Henry Samueli, co-chair and chief technologist of Broadcom Corp., showed several real-world examples of Broadcom-developed system-on-chips and called for better tool integration. "We are losing the war with device physicists," said Samueli. "They are able to build chips that are far more complex than our ability to design and verify such chips." Samueli showed several recent Broadcom SoCs incorporating analog and digital blocks created by different Broadcom design groups as well as cores from vendors Broadcom had recently acquired. He said in the design of a 16-million-transistor SoC Ethernet switch, his designers ran into several issues with EDA tools. The design required high capacity verification, power grid analysis, in-place optimization and routing, and emulation, he said. "Emulation was mandatory for this design," he said. Samueli said that the company prefers to use internal IP or, in extreme cases, will purchase IP companies rather than use third-party vendor cores. He said Broadcom does so because some IP companies may go out of business.