Silicon Investor (SI) -- The First Internet Community

STOCKTALK

We've detected that you're using an ad content blocking browser plug-in or feature. Ads provide a critical source of revenue to the continued operation of Silicon Investor. We ask that you disable ad blocking while on Silicon Investor in the best interests of our community. If you are not using an ad blocker but are still receiving this message, make sure your browser's tracking protection is set to the 'standard' level.

Technology Stocks : Rambus (RMBS) - Eagle or Penguin -- Ignore unavailable to you. Want to Upgrade?

To: Scumbria who wrote (44863)	6/18/2000 10:13:00 AM
From: Zeev Hed	Read Replies (1) \| Respond to of 93625

Scumbria, I am not a chip designer and have no idea how long it would have taken to come up with the solutions RMBS has selected, but to accelerate data transfer rate, I could come up with another few concepts (which probably will not work). For instance, you could have a cascade of few capacitors associated with each cell and have not just an on or off (or 1,0), but 16 levels readable (and "writenable") on each clock cycle (probably will suffer from lack of stability and refreshing problems). RMBS selected one (the DDR approach for a doubling and now the QSM approach for quad?) way and and solved all the associated problems this approach entails. As for your second request that I respond to your general post on infringements in the semi business, I have no answer. By the way, if I did not respond the first time, it was because I did not want to respond. Somehow, you assume I have a hidden "responsibility" or obligation to respond to every post, I do not. Zeev

To: Scumbria who wrote (44863)	6/18/2000 5:40:00 PM
From: John Walliker	Respond to of 93625

Scumbria, Do you remember the old days when BIOS settings on PC's allowed you program the first beat latency from the L2? As far as I can tell, Rambus' claim is the same technique, applied to DRAM. I think the obvious way then would have been to have a strobe signal for the output register of the SDRAM which was driven by the chipset with a configurable delay. The innovation was to put the programmable delay into the memory chip itself. Rambus needed to do this, as Ali Chen pointed out, to compensate for propagation delays on the bus and allow each bit to be slotted into its proper place. SDRAM could have been implemented with an extra strobe pin, as was done with some SSRAMs and FIFOs. However, putting the programmable delay onto the memory chip saves a pin. John