Hi all; Re Rambus' patent on programmable latency...
The troublesome wording in the most significant Rambus patent claim is as follows:
1. A synchronous semiconductor memory device having at least one memory section including a plurality of memory cells, the device comprising:
clock receiver circuitry to receive an external clock signal;
a register which stores a value which is representative of a delay time after which the memory device responds to a read request; and
a plurality of output drivers to output data after the delay time transpires and synchronously with respect to the external clock signal.
patents.ibm.com
The problem is that this patent wasn't filed until Nov 20, 1998. This is long, long after SDRAMs were already commonplace. But this is a continuation of previous patents:
This application is a continuation of application Ser. No. 08/798,520, filed Feb. 10, 1997, now U.S. Pat. No. 5,841,580, which is a divisional of application Ser. No. 08/448,657, filed May 24, 1995, now U.S. Pat. No. 5,638,334, which is a divisional of application Ser. No. 08/222,646 filed Mar. No. 31, 1994, now U.S. Pat. No. 5,513,327, which is a continuation of application Ser. No. 07/954,945, filed Sep. 30, 1992, now U.S. Pat. No. 5,319,755, which is a continuation of application Ser. No. 07/510,898 filed Apr. 18, 1990, now abandoned.
The above patents were filed as early as 1992, and that is where the claim of priority to SDRAM comes from.
I believe that the oldest of the Rambus patents that mentions adjustable latency in memory is 5319755, which was filed Sept 30, 1992, and issued June 7, 1994:
patents.ibm.com
This patent describes a memory where the access time is determined by a register in the memory chip. I believe that this is the detail that the SDRAM makers are running afoul of. Basically, when you buy "333" SDRAM from Micron, you can run it as "222" memory, if you modify a register bit in the memory. Doing this reduces the peak frequency that you can clock it at, so most people would leave this alone. But the fact that the access is adjustable means that the memory maker only has to make one memory chip, and then the users can use it in a variety of different combinations of access time and clock frequency.
The base patent for the technique that SDRAM uses to provide adjustable latency is this one, owned by Hitachi, but it is not written with the intent of making it understandable to those not familiar with the art. (I.e. mom and pop.) Filed Nov 15, 1989, and issued Feb 4, 1992:
patents.ibm.com
Of interest regarding synchronous static RAM:
Triad Semiconductors Inc., Static RAMs have on-chip address and Data Latches for Pipelining, EDN, Dec. 8, 1988, p. 116.
Leibson, Steven, SRAM's On-Chip Address and data Latches Boost Throughput in Pipelined Systems, EDN, Oct. 13, 1988, pp. 102-103.
-- Carl |
