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Technology Stocks : WDC/Sandisk Corporation -- Ignore unavailable to you. Want to Upgrade?

To: Ausdauer who wrote (12076)	6/20/2000 6:44:00 AM
From: limtex	Read Replies (1) \| Respond to of 60323

Aus - Any views on the new tiny Canon d-camera? Looks interesting to me. Handspring and Palm offering camera add-ons so looks like cameras might be a thing of the past just like film. I guess we ought to look forward to the new Nikon PDA incorporating voice an mobile internet and by the way is also a camera!! Could I ask you to list the top five d-cameras as you see it today. Best regards, L

To: Ausdauer who wrote (12076)	6/24/2000 10:38:00 PM
From: wily	Respond to of 60323

Ausdauer, Why is it that SDRAM you buy to upgrade your PC comes in those long licorice sticks... ...with 6 or 8 silicon chips soldered on, while flash comes in a tiny little package like CF and MMC? Is this because of the scalability of flash? I'm going to guess that the apparent difference in size is because of the packaging technologies and form standards being used. There is no critical space efficiency required of main memory for computers (less true for laptops), so the industry has probably been satisfied to stay with older packaging technologies and form standards to avoid the expense of changing. Backwards compatibility can count for a lot in manufacturing. But, I emphasize that this is a guess! Regarding scalability and margins (more guesses): Probably the biggest cost in bringing memory to market is wafer processing, followed by packaging. I don't know, but I'd be very interested to know, what the relative percentages are here. As for wafer processing, the number of good bits you can yield from a wafer is the main determiner of cost. Processing time (a reflection of how many "difficult" or long the steps there are) is probably second. The number of bits you can get on a wafer is determined by the basic cell size and is a function of what electronic components comprise the cell: SRAM has 6 transistors; DRAM a transistor and a capacitor; NAND Flash I'm not sure, but I know it has a field-effect transistor as part of it. Each of these memory types has a fairly standard characteristic cell size that is expressed as F(L^2), where L is the photolithography line-width being used (for example, SNDK's best now is 0.18um) and F is the multiple that represents the characterisitic size of the cell. Some of these F values are: DRAM = 8 NOR Flash = 12 SRAM = 180 The values for DRAM and NOR Flash I have seen stated by manufacturers. SRAM is a guess based on various data I've seen. These numbers can be used for figuring cell density, but you also have to consider that many companies, including Sandisk are making Flash that can store two bits per cell. It is more difficult to do this and results in a higher cost per wafer (30% is what Sandisk quotes in their 10K) but, assuming yields are the same as for single bit, you are doubling your output of bits -- so, say you get 100Gbits out of a single-bit wafer and it costs you $5000; for $6500 you get 200Gbits and the cost per Gbit has gone from $50 to $32.50 -- a savings of 35%. This also increases your capacity, enabling you to grab market share if others aren't making the same advances. Here is a table showing how cell density varies with form factor (F) and photolithography limit (L). It is based on a 1/4" X 1/4" memory array (which doesn't include the chip-space taken by the addressing logic). Sandisk says in their 10K that NAND Flash can be made smaller than NOR Flash, so I would guess that F for Sandisk memory cells would be somewhere around 10. Memory companies seem to guard carefully their current information about what cell densities they are achieving. Using the formula for cell size: Size = F(L^2) L F cell size cells Mcells per Mbits/array (um^2) per um^2 1/4"X1/4" @ 2bits/cell array .25 12 0.75 1.33 53.7 .25 10 .625 1.6 64.5 129 .25 8 0.5 2.0 80.6 .18 12 .389 2.57 103 .18 10 .324 3.09 124 248 .18 8 .259 3.86 155 .18 6 .194 5.14 207 .18 4 .130 7.72 311 .18 2 .0648 15.4 622 .13 10 .169 5.92 238 476 .12 6 .0864 11.6 466 .12 4 .0576 17.4 700 .12 2 .0288 34.7 1400 So, you can see that NAND Flash at F=10 and 2 bits/cell has an effective F of 5 which, compared to F=8 for DRAM is a 37% advantage. That probably contributes to the small size possible with Flash cards, but I think there is probably much less wasted space in the Flash packaging. Or maybe DRAM needs much more logic circuitry on the chip? Note also, that the chip size doesn't exactly represent the space taken up by the memory arrays. There is also addressing circuitry which may take up 25% of the chip space. I'm not sure what the actual number is. Here's some guesses on how much room there is for bits on a CF card. This is based on the assumption that it is 1 1/2" X 1 3/4" (the size of a matchbook, which I have -- not an actual CF, which I don't have). Assume: ==>F=10 ==>L=.18 ==>2 bits/cell ==>20% of the card is wasted space, i.e., not used by a memory or controller chip (WAG). ==>1/3 of remaining space occupied by the controller chip (WAG) ==>1/4 of memory chip space is devoted to addressing, etc. logic circuits Starting with 2.6in2, this leaves you with 1.05in2 for memory cells. That is the same as 16 1/4" X 1/4" arrays, and since each of these can hold 248Mbits, the capacity of the card would be 4Gbits or 0.5Gbytes or 500Mbytes. So, at .18um, the 192MB CF is only occupying 38% of the card's capacity -- according to my calculations and assumptions which could very well be flawed <g>. I would imagine that Sandisk would be making them with higher capacity if they could... As for margins, I think their gross margins on flash are slightly under 30% nowadays, whereas they were 0% for many years until the market started growing. Same cycles hit the DRAM industry -- that industry is notorious for wild swings because of the huge volatility in bit demand, manufacturing capacity and the difficulty in planning capacity and the expense to acquire it. I've been studying the Flash industry a little as a result of my interest in ECD (ENER) and the OUM technology they are developing with Intel. This could be an earthquake waiting to happen in the Flash industry, depending on how well they are able to implement multibit for OUM. 2 bits/cell I think would be easy. 4 bits might not be, but would be a knockout blow to the industry if they were able to do it. Since Intel supplies 25% of total Flash demand, 4 bit/cell OUM would quadruple their capacity and at the same time give them an "unfair" cost advantage. Even 2 bit/cell OUM would have a powerful effect, IMO. For OUM, F=6 and can possibly be reduced to 4. Of course, who knows if/when OUM will arrive? wily