United States Patent 6,064,627
Sakurai May 16, 2000
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Synchronous semiconductor memory device
Abstract
The present invention relates to a synchronous semiconductor memory device and an object of the present invention is to provide a synchronous semiconductor memory device in which an operation mode such as a set burst length would not be lost even at the power off. Here, the synchronous semiconductor memory device according to the present invention includes non-volatile memory for storing operation mode and controlling data reading operation and data writing operation in accordance therewith.
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Inventors: Sakurai; Mikio (Tokyo, JP)
Assignee: Mitsubishi Denki Kabushiki Kaisha (Tokyo, JP)
Appl. No.: 231397
Filed: January 12, 1999
U.S. Class: 365/233; 365/189.05; 365/230.06; 365/230.08
Intern'l Class: G11C 008/00
Field of Search: 365/233,230.06,230.08,189.05
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References Cited [Referenced By]
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U.S. Patent Documents
4698750 Oct., 1987 Wilkie 365/185.
5226015 Jul., 1993 Gotou et al. 365/230.
5390317 Feb., 1995 Weiss et al. 365/185.
5615151 Mar., 1997 Furuno et al. 365/185.
5694611 Dec., 1997 Matsubara 365/185.
5784328 Jul., 1998 Irrinki et al. 365/222.
5880992 Mar., 1999 Lee 365/185.
5880998 Mar., 1999 Tanimura et al. 365/189.
Foreign Patent Documents
63-206852 Aug., 1988 JP.
64-23548 Jan., 1989 JP.
3-35498 Feb., 1991 JP.
7-93970 Apr., 1995 JP.
8-124380 May., 1996 JP.
Primary Examiner: Nelms; David
Assistant Examiner: Auduong; Gene N.
Attorney, Agent or Firm: McDermott, Will & Emery
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Parent Case Text
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REFERENCE TO RELATED APPLICATION
This Application is a continuation of International Application No. PCT/JP96/02781, whose international filing date is Sep. 26, 1996 the disclosures of which Application are incorporated by reference herein. The benefit of the filing and priority date of the International and Application is respectfully requested.
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Claims
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1. A synchronous semiconductor memory device, comprising:
a memory storing data;
a clock signal buffer buffering an external clock signal to generate an internal clock signal;
an input buffering responsive to said internal clock signal and buffering an external control signal to generate an internal control signal;
an address buffer responsive to said internal clock signal and buffering an external address signal to generate an internal address signal;
a mode register in which operation mode can be set designating a reading procedure of said data from said memory and a writing procedure of external data into said memory;
a data reading circuit reading said data stored in said memory in response to said operation mode set in said mode register and in response to said internal clock signal and a read signal;
a data writing circuit writing external data into said memory in response to said operation mode set in said mode register and in response to said internal clock signal and a write signal;
a command decoder generating a mode set signal for setting said operation mode in said mode register in response to said internal control signal and generating said read signal and said write signal; and
a non-volatile memory storing said mode set signal and said internal address signal and supplying said stored mode set signal and said stored internal address signal to said mode register.
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Description
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BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to a semiconductor memory device, and more particularly to a synchronous semiconductor memory device operating in synchronization with a clock signal.
2. Description of the Background Art
In a synchronous semiconductor memory device (hereinafter referred to as an SDRAM) now available as a commercial product, Burst Length (BL), /CAS Latency (CL) and so on can be set in a mode register included in the device by a user at its use.
Here, Burst Length is a number of data read out or written into in sequence in one access cycle. In an SDRAM, BLs of 1, 2, 4 or 8 are available and some chips have a full page mode. /CAS Latency is a number of clock cycles elapsed from application of read instruction until an output of data from an output buffer. In an SDRAM, CLs=2, 3 in general are available and in some chips, CL=1, 4.
Though operation modes such as Burst Length and /CAS latency set in the mode register do not change until reset, at the power off the mode register is reset and the set information is lost.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a synchronous semiconductor memory device wherein a set operation mode is not lost even at the power off.
The object of the present invention is achieved by providing a synchronous semiconductor memory device including a memory storing data, a clock buffer generating an internal clock signal by buffering an external clock signal, an input buffer generating an internal control signal in response to the internal clock signal by buffering an external control signal, an address buffer generating an internal address signal in response to the internal clock signal by buffering an external address signal, a read circuit reading data from the memory, a write circuit writing external data into the memory, and, a non-volatile memory section storing an operation mode in accordance with the internal control signal and the internal address signal and controlling the read circuit and the write circuit in accordance with the operation mode.
A main advantage of the present invention lies in that the synchronous semiconductor memory device can be restarted in an operation mode stored in the non-volatile memory section without need of operation mode setting at the next power on after the power off, because the operation mode is stored in the non-volatile memory section.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a block diagram of a synchronous semiconductor memory device in accordance with a best mode for carrying out the present invention, and
FIG. 2 is a schematic block diagram of a memory section and a mode decoder shown in FIG. 1, referenced for describing their operations.
DESCRIPTION OF THE PREFERRED EMBODIMENTS
Hereinafter with reference to the drawings, a synchronous semiconductor memory device as a best mode for carrying out the present invention will be described. In the drawings, the same character indicates the same or corresponding element.
With reference to FIG. 1, the synchronous semiconductor memory device in accordance with the present invention includes a data input/output terminal 20, a memory cell array 35 storing external data supplied as an input to data input/output terminal 20, a row select circuit 33 selecting a row in memory cell array 35 to which data is to be written into or from which data is to be read out, a column select circuit 29 selecting a column to which data is to be written into or from which data is to be read out, an input buffer 3 buffering an external clock signal Ext. clk., a clock buffer 5 generating an internal clock signal Int. clk. by buffering an output signal from input buffer 3, an input buffer 1 generating an internal control signals by receiving and buffering external control signals such as a row address strobe signal /RAS, a column address strobe signal /CAS, a write enable signal /WE, or a chip select signal /CS in synchronization with internal clock signal Int.clk. generated by clock buffer 5, an address buffer 7 generating an internal address signal by receiving and buffering external address signal (A0-A11) in synchronization with the internal clock signal Int. clk., a column decoder 27 driving column select circuit 29 by decoding a column address signal in the internal address signal, a row decoder 31 driving row select circuit 33 by decoding a row address signal in the internal address signal, a command decoder 9 generating and supplying as an output a read instruction signal Read, a write instruction signal Write, and a mode register set signal MRS in accordance with a combination of row address strobe signal /RAS, column address strobe signal /CAS and write enable signal /WE sent to input buffer 1 as inputs, a mode register 13 including a /CAS Latency setting section 130, a Burst Length setting section 131, a burst type setting section (not shown) and so on, and setting an operation mode such as /CAS Latency or Burst Length in accordance with a combination of external address signal bits A0-A11 supplied as an input to address buffer 7 in response to an input of mode register set signal MRS, a memory section 11 storing the internal address signal and mode register set signal MRS for setting the operation mode, a mode decoder 12 decoding and supplying a signal stored in memory section 11 to mode register 13, a read control circuit 15 generating an output enable signal OEM and a read control signal in accordance with the operation mode set in mode register 13 and in response to internal clock signal Int. clk. and read instruction signal Read, a read circuit 17 reading out data stored in memory cell array 35 in response to the read control signal, an output buffer 19 being activated by output enable signal OEM and buffering and supplying as an output data read out by read circuit 17 to data input/output terminal 20, a write control circuit 21 generating a write control signal in accordance with the operation mode set in mode register 13, and in response to internal clock signal Int. clk. and write instruction signal Write, an input buffer 23 buffering external data supplied as an input to data input/output terminal 20 and a write circuit 25 writing into memory cell array 35 data supplied as an output from input buffer 23 in response to the write control signal.
FIG. 2 is a schematic diagram showing configurations of memory section 11 and mode decoder 12.
As shown in FIG. 2, memory section 11 includes, for example, two non-volatile memory elements 110 and 111 each storing 1 bit information, and mode decoder 12 includes an inverter, and an NAND circuit.
Next, the operation of the synchronous semiconductor memory device will be described.
When row address strobe signal /RAS, column address strobe signal /CAS, write enable signal /WE and chip select signal /CS are all supplied as an input to input buffer 1 in a logical low level state in response to the internal clock signal, command decoder 9 supplies, as an output, mode register set signal MRS to mode register 13.
The mode register set signal MRS is stored in memory section 11 until a next mode register set signal MRS is supplied as an output from command decoder 9.
Mode register 13 having received the mode register set signal MRS, stores in memory section 11 a combination of external address signal bits A0-A11 supplied as an input to address buffer 7 and sets /CAS Latency and Burst Length respectively in /CAS Latency setting section 130 and Burst Length setting section 131 according to the combination. In particular, Burst Length is designated by combination of external address signal bits A0, A1 and A2 and /CAS Latency is designated by combination of external address signal bits A4, A5 and A6.
Here, on receiving read instruction signal Read, read control circuit 15 controls read circuit 17 in accordance with /CAS Latency and Burst Length set in mode register 13 in synchronization with internal clock signal Int. clk. and supplies as an output, output enable signal OEM for activating output buffer 19.
On the other hand, on receiving write instruction signal Write, write control circuit 21 controls write circuit 25 in accordance with Burst Length set in mode register 13 in synchronization with internal clock signal Int. clk.
When the synchronous semiconductor memory device is powered off, /CAS Latency and Burst Length set in mode register 13 are lost. At the power on, however, /CAS Latency, Burst Length and so on are set again in mode register 13 to the same values as immediately before the power off in accordance with the mode register set signal MRS and the internal address signal stored in memory section 11.
Operations of memory section 11 and others will be described referring to FIG. 2.
Assume that memory section 11 includes two 1-bit non-volatile memory elements 110 and 111, for example, that store address information (X,Y). If (0, 0) is stored as (X,Y) at the power off, memory section 11 supplies (0, 0) as an output at the power on, and an output signal A from an inverter 120 of mode decoder 12 will be "1" and output signals B, C, and D from inverters 121, 122, and 123 will be all "0". Thus the operation modes such as /CAS Latency, which is determined by the signal A taking the value "1", are reset.
When (0, 1) is stored as (X, Y), only the output signal B from inverter 121 is "1". If (1, 0) is stored, only the signal C, and if(1, 1) is stored, only the signal D is "1".
Particularly, an EPROM (Electrically Programmable Read Only Memory), an EEPROM (Electrically Erasable and Programmable Read Only Memory) or the like can be used as the non-volatile memory elements 110 and 111. If the element is overridable, rewriting is possible for a number of times.
With the synchronous semiconductor memory device described above, troublesome setting of operation modes such as /CAS Latency at the power on can be avoided, because information for setting operation modes such as /CAS Latency and Burst Length is stored in memory section 11 including the non-volatile memory element.
In the foregoing, memory section 11 may be included in mode register 13 and stores mode register set signal MRS supplied as an input to mode register 13 and an output signal from mode decoder 12. The same advantages can be obtained as well when memory section 11 is in mode register 13 and stores an output signals from /CAS Latency setting section 130 and Burst Length setting section 131.
Although the present invention has been described and illustrated in detail, it is clearly understood that the same is by way of illustration and example only and is not to be taken by way of limitation, the spirit and scope of the present invention being limited only by the terms of the appended claims.
164.195.100.11
Comments?
Milo
Here's a list of SDRAM patents involving Hitachi.
164.195.100.11
Searching 1976-2000...
Results of Search in 1976-2000 db for:
sdram: 841 patents.
Hits 1 through 50 out of 841
PAT. NO. Title
1 6,075,901 Method and system for predictive encoding of arrays of data
2 6,075,899 Image decoder and image memory overcoming various kinds of delaying factors caused by hardware specifications specific to image memory by improving storing system and reading-out system
3 6,075,748 Address counter cell
4 6,075,393 Clock synchronous semiconductor device system and semiconductor devices used with the same
5 6,073,223 Memory controller and method for intermittently activating and idling a clock signal for a synchronous memory
6 6,073,206 Method for flashing ESCD and variables into a ROM
7 6,073,203 Method for the continuous readout of a data sequence from a memory
8 6,073,187 Controls and indicators available to a user for a secondary operational mode of a portable computer which is open or closed state of the computer case
9 6,072,744 Memory device having data bus lines of uniform length
10 6,072,743 High speed operable semiconductor memory device with memory blocks arranged about the center
11 6,072,742 Semiconductor memory device with a voltage down converter stably generating an internal down-converted voltage
12 6,072,729 Data-output driver circuit and method
13 6,072,699 Method and apparatus for matching trace lengths of signal lines making 90.degree./180.degree. turns
14 6,072,483 Active frame scroll interface
15 6,072,233 Stackable ball grid array package
16 6,070,539 Variable rate agricultural product application implement with multiple inputs and feedback
17 6,070,227 Main memory bank indexing scheme that optimizes consecutive page hits by linking main memory bank address organization to cache memory address organization
18 6,070,217 High density memory module with in-line bus switches being enabled in response to read/write selection state of connected RAM banks to improve data bus performance
19 6,070,215 Computer system with improved transition to low power operation
20 6,070,182 Data processor having integrated boolean and adder logic for accelerating storage and networking applications
21 6,069,829 Internal clock multiplication for test time reduction
22 6,069,815 Semiconductor memory having hierarchical bit line and/or word line architecture
23 6,069,508 Clock generating circuit having high resolution of delay time between external clock signal and internal clock signal
24 6,069,507 Circuit and method for reducing delay line length in delay-locked loops
25 6,069,506 Method and apparatus for improving the performance of digital delay locked loop circuits
26 6,069,504 Adjustable output driver circuit having parallel pull-up and pull-down elements
27 6,067,649 Method and apparatus for a low power self test of a memory subsystem
28 6,067,632 Clock-synchronized memory device and the scheduler thereof
29 6,067,583 Modular, reconfigurable components methods for wireless data transfer between a computer and a communications system
30 6,067,507 Method in an integrated circuit (IC) manufacturing process for identifying and redirecting IC's mis-processd during their manufacture
31 6,067,273 Semiconductor memory burst length count determination detector
32 6,067,272 Delayed locked loop implementation in a synchronous dynamic random access memory
33 6,067,270 Multi-bank memory devices having improved data transfer capability and methods of operating same
34 6,067,260 Synchronous semiconductor memory device having redundant circuit of high repair efficiency and allowing high speed access
35 6,067,255 Merged memory and logic (MML) integrated circuits including independent memory bank signals and methods
36 6,065,122 Smart battery power management in a computer system
37 6,065,102 Fault tolerant multiple client memory arbitration system capable of operating multiple configuration types
38 6,065,093 High bandwidth narrow I/O memory device with command stacking
39 6,065,088 System and method for interrupt command queuing and ordering
40 6,065,077 Apparatus and method for a cache coherent shared memory multiprocessing system
41 6,065,066 System for data stream packer and unpacker integrated circuit which align data stored in a two level latch
42 6,065,027 Data processor with up pointer walk trie traversal instruction set extension
43 6,064,948 Tester systems
44 6,064,627 Synchronous semiconductor memory device
45 6,064,625 Semiconductor memory device having a short write time
46 6,064,621 Multi-bank clock synchronous type semiconductor memory device having improved memory array and power supply arrangement
47 6,064,619 Synchronous dynamic random access memory in a semiconductor memory device
48 6,064,617 Method and apparatus for strobing antifuse circuits in a memory device
49 6,064,407 Method and apparatus for tiling a block of image data
50 6,061,786 Processor configured to select a next fetch address by partially decoding a byte of a control transfer instruction |
