Silicon Investor (SI) -- The First Internet Community

STOCKTALK

We've detected that you're using an ad content blocking browser plug-in or feature. Ads provide a critical source of revenue to the continued operation of Silicon Investor. We ask that you disable ad blocking while on Silicon Investor in the best interests of our community. If you are not using an ad blocker but are still receiving this message, make sure your browser's tracking protection is set to the 'standard' level.

Technology Stocks : Intel Corporation (INTC) -- Ignore unavailable to you. Want to Upgrade?

To: Paul Engel who wrote (104834)	6/24/2000 3:35:00 PM
From: Cirruslvr	Read Replies (1) \| Respond to of 186894

Paul - RE: "Doubling the data path and address lines form 32 to 64 will have a SEVERE impact on die size. AMD may have implied that a 64 bit SludgePumper on a 0.13 micron process would be 5% bigger than a 0.18 micron AThwiper." Nope. "Adding 64-bit capabilities increases the die size only 5% over the approximately 104 sq. mm that a 32-bit Athlon requires, using a 0.18-micron process, Lapinski said." ebnews.com When this article came out last year, I remember you and Saturn V were wondering how AMD could claim this because both of you thought the extension to 64bit required much more die space.

To: Paul Engel who wrote (104834)	6/24/2000 4:17:00 PM
From: Dan3	Read Replies (2) \| Respond to of 186894

Re: Doubling the data path and address lines form 32 to 64 will have a SEVERE impact on die size... Surprise! External Data and cache paths for Pentium, Pentium II, Pentium III, Cyrix, K6, K6-2, Celeron, Athlon, Duron are all 64 bit already! Have been since the original Pentium came out. Additional address pins are needed only for as much additional physical memory is supported - 4 more pins would allow 16 times the physical memory of present chips. Internal data paths in the ALU will be wider - that's what adds 5% to the die size. Dan