Net processor makers clash over next-generation DRAM
By Craig Matsumoto
EE Times
(06/26/00, 3:16 p.m. EST)
eetimes.com
SAN JOSE, Calif. ? Rambus Inc.'s DRAM interface is gaining favor in networking applications, but some designers of network processors say that the interface's shortcomings ? both its technology and in terms of the Rambus business model ? are driving them to seek out other architectures.
In fact, while such companies as Vitesse Semiconductor Corp. and MMC Networks Inc. are embracing Rambus, executives building network processors at Agere Inc. and Cisco Systems Inc. are investigating whether an alternative DRAM interface can be developed.
"I've said publicly and internally: Our team hasn't been allowed to use Rambus for four years," said Bill Jennings, a manager who led development of an internal network processor at Cisco. Cisco has engaged two vendors to help develop a commodity memory more suitable for networking.
For its part, Agere (Austin, Texas), recently acquired by Lucent Technologies, has developed a memory interface on its own as a hedge in case no better alternative emerges.
Elsewhere, too, interest has arisen in a DRAM interface tailored for networking. "Right now, it's just starting to bubble up," said Marc Miller, director of product marketing for the Internet computing division of LSI Logic Corp. An ally of both the Rambus and SDRAM camps, LSI Logic expects to work with emerging network DRAM efforts as well.
Alternative weighed
And officials at HotRail Inc. (San Jose, Calif.), which has developed calibration circuitry to improve interconnect speeds, confirmed they are negotiating a licensing deal with a memory vendor that intends to produce a network-minded alternative to the Rambus interface.
At issue is Rambus' PC-centrism. Development of the Rambus interface began nearly a decade ago, when the PC was the obvious target market. That meant Rambus was built to optimize cache-line transfers, said Mike Hathaway, chief technical officer at Agere.
Cisco's Jennings agreed, noting that in packet processing, the transient nature of packet headers makes cache flushes too costly in terms of time. "In this model, Rambus actually gets in the way," he said.
Jennings said Rambus works fine for control-plane functions, which tend to be handled by a general-purpose processor. Those functions include the management of interfaces and data paths ? software-based functions that resemble traditional computing.
But Rambus falls short in other areas, at least for Jennings' needs. The burst nature of the interface doesn't suit routing-table searches, for example, in which the processor does a chain of searches down a "tree" of entries. Each search retrieves a small chunk of data ? 4 to 32 bits in some cases ? which is used to determine parameters for the next search.
Here, Cisco needs guaranteed short latency times in order to "walk the tree" quickly enough, and burst mode doesn't fit the bill, Jennings said.
He also takes issue with the Rambus architecture's use of phase-locked loops. "When you use PLLs, your yields go down [because of the parts' analog nature], and the number of interfaces you can support on a chip goes down," he said. "I'm thinking about internally getting away from using PLLs."
Specialty memories have been developed for networking, but Jennings and Cisco want to use a cheap, commoditized memory. To that end, Cisco has engaged two DRAM vendors, which Jennings would not identify, to develop memory interfaces geared especially for networking.
"The industry in general hasn't moved to build anything but specialty memory for datacom," he said. "So two of the vendors have acknowledged that."
A commodity part would obviously save the cost of Rambus' licensing fees, but it would also allow Cisco to offer more options with its boxes.
For example, Jennings described how Cisco could more easily offer upgradable routers. The company's prices today are driven by memory configuration, Jennings said, so that a low-end box normally is loaded with commodity memory while a higher-end box has better-performing specialty memory. Using one type of memory for both ? something cheap but still effective ? might let Cisco unify the boxes into an upgradable architecture, he said.
Creative limits
Jennings also would prefer to work with an architecture more open than Rambus'. "Their business model is not very open, and that tends to limit the creativity and openness in the ecosystem of joint development," he said. "You wind up locking yourself into a very limited number of options."
Given Jennings' grievances, it's no surprise the first version of his network processor for Cisco ? based on an architecture called parallel express forwarding (PXF) ? used commodity memory. "Part of the design was to use inexpensive and dense memory ? inexpensive in terms of power and cost," he said. Rambus failed on both accounts, he said.
Agere has gone so far as to work on its own DRAM interface, as Hathaway mentioned at the Gigabit Ethernet conference in March. The company doesn't necessarily want to own a new memory interface, but the standards being offered ? Rambus' in particular ? are geared too much toward the PC, he said.
Still, it will take time for Agere or anyone else to turn around an interface. "In the meantime, you use whatever off-the-shelf technology you can," Hathaway said, noting that his company is investigating the use of RDRAM as well as Fujitsu's Fast Cycle RAM (FCRAM).
Some network-processor organizations have embraced Rambus. Sitera Inc. (Longmont, Colo.), now a part of Vitesse, believes that Rambus "will be engineering-best-practices for the next coming years," said Wade Appelman, vice president of Vitesse's Advanced Networked Products Division.
The difference of opinion can partly be explained by architecture, since Sitera's processor has some features that make Rambus a natural fit. For example, its lookup-accelerator coprocessor is optimized for receiving 32 bytes at a time, a perfect mate to Rambus' cache-minded interface, which grabs data 32 bytes at a time.
Appelman said that Rambus' PC-centric nature isn't a stumbling block, considering that networking requires moving large amounts of data, much as PC graphics processing does. "On the PC side, the data is generally in bursts, lines of graphics. On the networking side, you're generally bursting packets," Appelman said. And only Rambus can meet line speeds of 2.5 Gbits/second, the current mainstream for network core routers, he said.
Finally, Appelman contended that Rambus is a good fit for both packet queuing, which requires fast access and is typically handled with SRAMs, and tables, which require large densities normally found in DRAMs. "What Rambus allows you to do is keep all that in one memory system. It's still a pricing premium in terms of a DRAM system interface, but it's 10 percent the cost of SRAM," he said.
Should even Rambus prove not fast enough, the answer so far is to simply add more channels, said Cindy Lindsay, director of partner programs for Vitesse.
"I know of one design that has eight Rambus channels," she said. "These are OC-192-and-above chips. Rambus has the next-generation designs in process."
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