SI
SI
discoversearch

We've detected that you're using an ad content blocking browser plug-in or feature. Ads provide a critical source of revenue to the continued operation of Silicon Investor.  We ask that you disable ad blocking while on Silicon Investor in the best interests of our community.  If you are not using an ad blocker but are still receiving this message, make sure your browser's tracking protection is set to the 'standard' level.
Politics : Formerly About Advanced Micro Devices -- Ignore unavailable to you. Want to Upgrade?


To: Elmer who wrote (117961)6/28/2000 12:17:00 AM
From: Petz  Read Replies (1) | Respond to of 1576197
 
Elmer, <considering they [Intel] have recently announced 4 new mega fabs and perhaps a fifth soon>

Just curious, when building a new fab how strictly is the "copy exactly" philosophy carried out? It seems like steppers, and other machines are always getting more and more accurate, HVAC systems get improved year by year, etc. But if Intel has to copy "exactly," they have to stick with old equipment.

Petz



To: Elmer who wrote (117961)6/28/2000 12:32:00 PM
From: pgerassi  Read Replies (1) | Respond to of 1576197
 
Dear Elmer:

You have stated that it is better. The "it is better" has failed to show up in the marketplace yet. The last steppings have not shown much "improvement". When this is apparent, I will admit to it.

The change in marketable speed grades upward, or "Bins" as you put it, does not change the fundemental speed yield curve as it can happen overnite while, process changes must take 8-12 weeks to even show up. If the marketable speeds, change upward, the overall yield of a batch changes downward. by simply changing a marketable bin into an unmarketable bin. Now, nothing has changed in the production pipeline, but the ratio of shipped chips to total chips declines. This is where the latency of the production pipeline becomes the problem.

Now as to your "attempts to increase the speed distribution curve does not impact yields" goes against historical facts. A case in point is the pushing of the K6-2 from 350 to 400MHz. This caused a new stepping to be tried. It worked in the lab but, it reduced the overall shipping yield. Whether it was that some runs were ok but others were very bad, or simply the percentage of bad chips increased greatly, is not the point. It definitely impacted yields.

To increase the speed distribution can be taken in one of three ways, better design, better materials, better ways of using existing materials. Well, a better design, could introduce an error that causes a yield crash. A number of historical cases are well known on this one. A better group of materials, could cause some interaction difficulties, require tolerances that are too low to meet, or need steps that one has little experience in. There are cases of this happening in the past, usually happening in pilot lines. There are cases of things that worked ok in the labs but, can not be duplicated on the production floor. This is also true for the third case, better use of materials. The notching process of Intel's would be one example of this. The jury is still out on this one due to its current use. In five to ten years, we probably will know for sure, if it falls into the successful category and is duplicated industry wide, or if it is one of those things people will classify as a Big Mistake. There are cases where a new technique just did not work well. So the case is made that attempts to increase the speed distribution, or as statisticians say, shift the speed yield PDF to the right, can impact yields.

The visability is now higher than it was before for Intel because the competition with AMD no longer allows schedule slippage to covered up by not releasing till everything is running smoothly. AMD has suffered this continuously for years, now Intel will have to learn to deal with it too.

As for the simple becoming complicated, you do not seem to listen to simple truths but, seem to want proofs of them. Well, proofs take time and space. You can not have it both ways.

Pete