Silicon Investor (SI) -- The First Internet Community

STOCKTALK

We've detected that you're using an ad content blocking browser plug-in or feature. Ads provide a critical source of revenue to the continued operation of Silicon Investor. We ask that you disable ad blocking while on Silicon Investor in the best interests of our community. If you are not using an ad blocker but are still receiving this message, make sure your browser's tracking protection is set to the 'standard' level.

Politics : Formerly About Advanced Micro Devices -- Ignore unavailable to you. Want to Upgrade?

To: EricRR who wrote (118026)	6/28/2000 11:20:00 AM
From: Elmer	Read Replies (1) \| Respond to of 1576164

Re: "Elmer I always assumed that a shrink naturally would lead to better binsplits. Why do you not presume this? Am I confusing a process shrink with a layout shrink?" We were talking about adversely effecting yields, which it shouldn't. Regarding a process shrink vrs a layout shrink, I have always heard of a layout shrink referred to as a "compaction" and an optical shrink simply referred to as a shrink. For example, when the PPro first came out, it was originally layed out on a .65u process but because the.35u process was nearly ready they did a "dumb" shrink and tried it on .35u as well. It worked so well they went with the .35u instead of the .65u process but the layout was never really optimized for .35u. It wasn't until PII (Klamath) that the layout was done around .35u design rules. CuMine differs from Katmai by not only the addition of the on die L2, but the layout takes advantage of an additional metal layer not available on .25u process. A shrink of a .25u CuMine to .18u wouldn't have been able to use the additional metal layer. EP