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Politics : Formerly About Advanced Micro Devices -- Ignore unavailable to you. Want to Upgrade?

To: milo_morai who wrote (119112)7/4/2000 1:51:49 AM
From: milo_morai  Respond to of 1578188
 
Chapter 4 Signal Descriptions 17
21910E — March 2000 AMD-751™ System Controller Data Sheet
Preliminary Information
4 Signal Descriptions
4.1 Processor Interface Signals
4.1.1 CLKFWDRST (Clock Forward Reset)
Output
Summary CLKFWDRST resets the source-synchronous clock circuitry for
the processor.

Driven This signal is negated by RESET#. It is asserted off the rising
edge of SYSCLK.
4.1.2 CONNECT (Connect)
Output
Summary CONNECT is an output from the AMD-751 system controller
and is used for power management and source-synchronous
clock initialization at reset.
Driven This signal is negated by RESET#. It is asserted off the rising
edge of SYSCLK.
4.1.3 PROCRDY (Processor Ready)
Input
Summary PROCRDY is an input to the AMD-751 system controller and is
used for power management and source-synchronous clock
initialization at reset.
Sampled This signal is sampled on the rising edge of SYSCLK.

amd.com

20 Signal Descriptions Chapter 4
AMD-751™ System Controller Data Sheet 21910E — March 2000
Preliminary Information
4.1.9 SDATA[63:0]# (Processor Data Channel)
Bidirectional
Summary The SDATA[63:0]# channel is the bidirectional interface to and
from the processor and system for data movement. Data is
skew-aligned with either SDATAINCLK[3:0]# or
SDATAOUTCLK[3:0]#. Each edge is used to transfer data.
Note: In/Out is relative to the processor.
The SDATA[63:0]# channel connects to the 64-bit data channel
of the processor. Each of the four words of data that comprise
this channel is quali f ied by a corresponding clock
(SDATAINCLK[3:0]# or SDATAOUTCLK[3:0]#).
Driven, Sampled, and
Floated
As Outputs: The AMD-751 system controller drives the
SDATA[63:0]# channel with valid data on each edge of the
system address clocks (SDATAINCLK[3:0]#).
As Inputs: During write cycles, the AMD-751 system controller
samples the SDATA[63:0]# channel on each edge of
SDATAOUTCLK[3: 0]#.
SDATA[63:0]# is floated out of RESET#. It remains floated
except when driven with write data by the processor, by read
data (writeback data) from the cache, or by read data from the
AMD-751 system controller.
4.1.10 SDATAINCLK[3:0]# (System Data In Clock)
Output
Summary SDATAINCLK[3:0]# is the single-ended source-synchronous
clock driven by the AMD-751 system controller to transfer data
on SDATA[63:0]#. Each 16-bit data word is skew-aligned with
this clock. Each edge is used to transfer data.
Driven This signal is driven inactive (negated) when the CLKFWDRST
signal is active (true). When CLKFWDRST is deasserted,
SDATAINCLK# runs continuously.

Milo


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