SI
SI
discoversearch

We've detected that you're using an ad content blocking browser plug-in or feature. Ads provide a critical source of revenue to the continued operation of Silicon Investor.  We ask that you disable ad blocking while on Silicon Investor in the best interests of our community.  If you are not using an ad blocker but are still receiving this message, make sure your browser's tracking protection is set to the 'standard' level.
Technology Stocks : CYPRESS Semiconductor (CY) -- Ignore unavailable to you. Want to Upgrade?


To: Steve Hursey who wrote (2373)7/20/2000 8:42:05 PM
From: rinv  Respond to of 2694
 
defects in the raw silicon wafer are only one class of
"defects" causing yield loss -- moreover -- silicon
defects introduced during implant/diffusion are generated
which may not even be affected by native defects in the
starting material. ive dealt mostly with photolith and etch
related defects which are caused by improper exposures,
CDs etc and overetch/underetch of poly/metals, etc. id say
these account for more than 75% of what ive seen in my
work. other silicon defects that ive worked with are related
to esd which will blow holes in oxide and cause pitting in
silicon as you deconstruct a failed chip during failure
analysis.

the thing is, the high temp steps would probably anneal
out any native defects of consequence anyways.

but after all this, why is CY=IDTI-27 ????!!!!????
it never has anything todo with technology...

-rinv