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Technology Stocks : Intel Corporation (INTC) -- Ignore unavailable to you. Want to Upgrade?

To: pgerassi who wrote (105379)	7/8/2000 9:57:28 PM
From: Dan3	Read Replies (1) \| Respond to of 186894

Re: Even Intel's benchmarks show Athlon to be faster and cheaper than Cmine... Pete, That benchmark is inoperative. The operative benchmarks are being written now and will be released as soon as they can find anything that runs faster on PIV than Tbird. :-) Dan

To: pgerassi who wrote (105379)	7/8/2000 10:02:28 PM
From: Elmer	Read Replies (3) \| Respond to of 186894

Pete, as you no doubt know, AMD is ashamed of their benchmark scores and therefore use unavailable motherboards, unavailable versions of DirectX and unavailable versions of the graphics card drivers in a desperate attempt to boost their scores to acceptable levels. This is understandable considering their claims of 7th generation technology fell flat when Intel's old 6th generation CuMine easily beat them in virtually all benchmarks. When coming out with an enhanced version of the Athlon, TTurd, AMD was under the gun to show benchmark improvements, thus the cheating with the aforementioned unavailable hardware and software. It truly must be a shock when Intel's CuMine/i815 processor/chipset honest benchmarks pull even with AMD's phoney benchmarks. Well, it's understandable. The TTurd has a rather backward cache design. The claims of "fullspeed" hardly tell the true story when you consider that the 64 bit internal "fullspeed" databus needs 4 times the cycles to equal a single 256bit "fullspeed" CuMine cycle. And that much acclaimed copper process that yielded absolutely ZERO speed increase over aluminum. Don't worry... You'll soon see what a real 7th generation processor is really like..... EP

To: pgerassi who wrote (105379)	7/9/2000 12:07:20 AM
From: milo_morai	Respond to of 186894

Pete Elmer here's that info on Piii's cache "To: Saturn V who wrote (82709) From: Tenchusatsu Sunday, Dec 12, 1999 5:34 AM ET Reply # of 119756 Saturn's right, Elmer. If I remember correctly, MPR says "Technically, Coppermine's L2 cache is half-speed." This is because the cache transfers a cacheline (32 bytes) every other clock. It's no big deal, though. That back-side bus interface is so wide, an entire cacheline gets transferred in one clock, instead of four clocks on the older BSB interfaces. Perhaps the old BSB interface also had one dead clock in-between cacheline transfers, and this dead clock carried over into the Coppermine cache. Tenchusatsu Message 12262688 Milo P.S. I just wanted you to know the FACTS