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Technology Stocks : Rambus (RMBS) - Eagle or Penguin -- Ignore unavailable to you. Want to Upgrade?

To: Tenchusatsu who wrote (47111)	7/12/2000 9:04:38 PM
From: Dan3	Read Replies (1) \| Respond to of 93625

Re: First of all, Coppermine has a 256-bit wide connection between the core and L2 cache... Sorry, but that does reinforce my point. Willamette will have an internal bus at least as wide as Coppermine. That's why the volume chipset for Willamette (Tulloch) isn't going to be stuck with Rambus.> How do you know both of these "facts"? IMHO, because of the importance of latency in higher speed systems, the delays inherent in the serialization process used by Rambus will make it less and less competitive as system speeds increase. Rambus chips have to read 8 cells for each data line, packetize the data, then send it. There is no way for them to compete with chips that just read the cells and send. They can double the clock speed by serializing the data but the additional control and ground lines needed end up doubling the width of the traces on the board so there is no net gain in data rate per cm of board used by the traces and you're still stuck with the latency penalty from reading 8 cells and packetizing them. Dual DDR channels will fill the 256 bit cache line of coppermine in a two memory bus clocks, with the first 32 bytes ready in a half memory bus clock. DDR in sampling video cards is already running at a 333MHZ rate (166 clock, so called PC2600) - at cas 2 that's 21 clocks at 1 GHZ till there are 16 bytes in the cache, and 9 more to fill the line. So it's 21 clocks to end the stall and 30 clocks to fill a line. Dual PC800 rambus takes a flat 40 clocks to read the cells and put the packet together then another 1.5 clocks to put the first 4 bytes into the cpu, with 10.5 more needed to fill the line for a total of 52 clocks to fill a cache line. It's just a bad idea. Dan