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To: Tenchusatsu who wrote (105617)7/13/2000 1:59:43 PM
From: Tony Viola  Respond to of 186894
 
Tenchusatsu, >On page 2 of the PDF doc, the table mentions a future model "TBD" with an 800 MHz Xeon, 2M of L2 cache.

Of course, when that spec. sheet was written, the 800 MHz 6000R could have been still TBD. Intel canceled the 800 MHz Cascades last week.

At least this wasn't a 256K Coppermine being used in a 4-way SMP configuration. That would be stupid, to say the least, if it's even possible.

Good point. So it almost has to be 800 MHz, 2 MB Xeons, or Cascades, which is canceled. Maybe IBM announced a product they don't really have? Oh, I know. They overclocked the 700s!

Tony