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To: EricRR who wrote (2897)	7/29/2000 9:44:36 PM
From: Bilow	Read Replies (1) \| Respond to of 275872

Hi RatbertRyand; The best thing about a deep pipeline is the high clock rate that goes with it. So what if you end up with a processor that doesn't perform nearly as many instructions per clock. The average guy who buys a machine only knows that it is a "700MHz" computer, not what it benchmarks out at. -- Carl

To: EricRR who wrote (2897)	7/30/2000 9:52:27 AM
From: Scumbria	Respond to of 275872

Ratbert, Where did you here 28 stages? I thought it was 20. The full Willy pipeline is 28 stages. The 20 stage number refers to the length between the trace cache and completion, but trace cache misses require an extra eight stages. Every trace cache miss throws eight bubbles into the pipeline. Also you said in another post that the double pumped ALU was a big mistake because it prevents higher frequencies. Wasn't the double pumped ALU needed to prevent pipeline stalls? The double pumped ALU removes some bubbles caused by data being forwarded from one instruction to the next, or possibly from the cache. The problem it causes is that clock skew and jitter become exponentially more serious as the clock speed increases. So having a double speed clock severely cramps the headroom for MHz improvement. Scumbria