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Technology Stocks : Advanced Micro Devices - Moderated (AMD) -- Ignore unavailable to you. Want to Upgrade?

To: THE WATSONYOUTH who wrote (2914)	7/31/2000 1:28:10 AM
From: THE WATSONYOUTH	Read Replies (2) \| Respond to of 275872

Re: "I looked at the patent very briefly. Sorry to say but it is probably worthless. I'll look at it more carefully Sunday evening. I'll have to crawl through the whole thing." In my opinion, this is a worthless patent. They claim two benefits. 1) reduced S/D junction capacitance. 2) reduced contact resistance. As for 1) I believe there are better more straight forward ways to minimize junction capacitance. Obviously, reducing the deep junction area will help. To that effect, one should use aggressive overlay and image tolerances to minimize the size of the active silicon area. As I have stated before, AMD (at least in the classic Athlons out of Austin) is NOT using a very aggressive set of ground rules. I hope Mustang will be built with more aggressive ground rules. Second, the use of local interconnect allows the S/D contacts to be borderless to the edge of the shallow trench isolation which reduces the size of the required active area thus minimizing junction capacitance. Intel does not use this local interconnect process but instead uses fully landed contacts which require more active silicon area. However, Intel is very careful to engineer their S/D junctions and wells to minimize junction capacitance. This is accomplished by very particular dopant concentration profiles. I think AMD would be better served to simply minimize junction area by straight forward although brute force aggressive scaling in conjunction with optimized S/D and well profiles.If they do this, they will always have an edge over Intel in this respect because the borderless local interconnect allows for a smaller active silicon area. With regard to contact resistance, it is not at all clear that this disclosure would actually reduce it. Elevated contact resistance is most often associated with interfacial problems somewhere in the contact stack. If it was simply a function of the size of the contact, how could one continually scale to smaller dimensions. It is not clear one would form good CoSi2 on the sidewall contact described in this patent nor is it clear you would have a clean interface between the silicide and the contact stud. I could envision higher contact resistance even with larger contact area. Also, the processing sequence outlined to accomplish this structure is overly complicated given the dubious benefit. It is, in my opinion, a very poor tradeoff which AMD would not be foolish enough to try. THE WATSONYOUTH