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To: Dave B who wrote (48682)	8/2/2000 2:19:32 AM
From: jim kelley	Read Replies (1) \| Respond to of 93625

Thanks for the post Dave. So much for the narrow data window theory! The lying that is going on is phenomenal. I guess too many people agree that business is war.

To: Dave B who wrote (48682)	8/2/2000 4:14:55 AM
From: Bilow	Respond to of 93625

Hi Dave B: Cool! A technical post to respond to! Re: "Two observations - first, the new package Samsung is referencing is a CSP - the same used to package RDRAM today, and that the DDR proponents insist is not cost effective." Which technology is cost effective is something that changes with time. PLCCs, for example, weren't cost effective in 1965. When the CSP becomes a cost effective package, the DDR people (i.e the memory industry free of the fascist boot of Intel/Rambus) will use it. I have no doubt at all that CSP will be used a great deal in the future. Engineering is mostly a matter of choosing cost effective solutions to problems, but the best solutions change with time. -- Carl

To: Dave B who wrote (48682)	8/2/2000 4:31:39 AM
From: Bilow	Respond to of 93625

Hi Dave B; Data window calcs for DDR and RDRAM... This is in re: "Second, if you look at the RDRAM data sheet, you'll see that the data valid window at 800 MHz is 630 ps, and at 1066 MHz it is 460 ps. ..." First of all, the numbers are wrong. He is probably looking at the 1066MHz part specs, but we are comparing chips shipping in 2000, not 2001. Not that it makes any difference, PC266 has timing margins that are about 4x easier than PC800. Second, the guy only uses one number for each frequency, but there are actually two, one for reading the other for writing. The correct calculations, for a couple of Samsung 128Mbit memories, one DDR, the other RDRAM, follow. Third, the guy shouldn't be talking about percents as far as ease of design. Propagation delays in chips are measured in nanoseconds (ns) or picoseconds, not percentages. Fourth, that the RDRAM specs are tighter is a disagreeable thing for design engineers. It means that the stuff is harder to design. Arguing that this is some sort of great advantage for RDRAM is like arguing that replacing 64 city buses each capable of reaching 55 miles per hour with 16 magnetic levitated trains, each capable of reaching 220 miles per hour is a good idea. The trains are built to tighter tolerances, so they must be better, right? And cheaper, too? Life just isn't that simple. For real engineers (as opposed to ivory tower intellectual engineers) tight tolerances are difficult, expensive, and prone to breakdown. In other words, not robust. Anyway, the calculation for PC266 memory... Samsung DDR SDRAM Output (i.e. read) data valid time calculation: Calculation Description Result ------------------ ----------------------- ------ tCK 7.5ns Clock cycle time 7.5ns tCL 0.45 * tCK Clock low level width 3.38ns tCH 0.45 * tCK Clock high level width 3.38ns tHP tCL min or tCH min Clock half period 3.38ns tQH tHP min -0.75ns Output DQS valid window 2.63ns Input (i.e. write) data valid time calculation: (i.e. setup and hold) Calculation Description Result ------------------ ------------------------- ------ tDS 0.5ns DQ & DM setup time to DQS 0.5ns tDH 0.5ns DQ & DM hold time to DQS 0.5ns tVALID tDS + tDH Time data must be valid 1.0ns tWDINV tHP - tVALID Time data may be invalid 2.38ns Note: tVALID and tWDINV are my names for those calculated timing values, you won't find them in the data sheet. The other parameters are in there. Samsung PC800 RDRAM Output (i.e. read) data valid time calculation: Calculation Description Result ------------------ ----------------------- ------ tCYCLE 2.5ns CTM/CFM cycle time 2.50ns tQmin -0.26ns Minimum CTM to DQA/DQB -0.26ns tQmax 0.26ns Maximum CTM to DQA/DQB 0.26ns tRDINV tQmax - tQmin Read data invalid 0.52ns tHP tCYCLE * 50% Clock half period 1.25ns tQH tHP min -tRDINV Output DQS valid window 0.73ns Input (i.e. write) data valid time calculation: (i.e. setup and hold) Calculation Description Result ------------------ ------------------------- ------ tS 0.2ns DQA/DQB/ROW/COL to CFM setup 0.20ns tH 0.2ns DQA/DQB/ROW/COL to CFM hold 0.20ns tVALID tS + tH Time data must be valid 0.4ns tWDINV tHP - tVALID Time data may be invalid 0.85ns I've been a bit liberal in assuming that tHP is 50% of tCYCLE. I'm not sure if this is the correct number. If the percent is lower, then the RDRAM numbers get smaller (and hence more difficult). That is probably where he gets the 630ps number. The results: Reading data out of DDR is considerably easier than reading data out of RDRAM. This is consistent with our human experience. It is easier to read the numbers on the boxcars when the train is going slowly by, not when it is going fast. No surprises here. DDR keeps has valid data for 2.63/0.73 = 3.6 times as long as RDRAM. This means that it is easier to read data out of DDR than to read data out of RDRAM. Writing data into DDR is considerably easier than writing data into RDRAM. Write data may change anywhere in a 2.38ns window with DDR, but RDRAM's window, at 0.85ns, is smaller by 2.8 in ratio. This is consistent with human experience. It is easier to thread a slowly moving needle than it is to thread one that is moving quickly. So the DDR device, at PC266, provides valid data for 2.6ns. The chipset has to capture data in this window. On the other hand, the chipset has a 2.4ns window in which to modify data being written to the part. These two numbers, 2.6ns for reads and 2.4ns for writes, are the targets that the chipset designers have to shoot for. Engineers like big targets. Big targets are easy to hit, and that means cheap to build. For example, William Tell would have loved to have had a pumpkin sized apple handy. Samsung data sheet references: (DDR) usa.samsungsemi.com (pages 52, 45) (RDRAM) usa.samsungsemi.com (pages 46, 48, 49) -- Carl

To: Dave B who wrote (48682)	8/2/2000 4:42:16 AM
From: Bilow	Read Replies (1) \| Respond to of 93625

Hi Dave B; Re: "Of course the argument will be made that if RDRAM can have 50% data valid window, then so can DDR. That's true, if they choose to implement more RDRAM technology in DDR. Already they've used differential clocks, small swing signals, and transmit DLL's. They could add receive DLL's, output driver calibration, matched impedence drivers - any number of things that are available from the Rambus patent portfolio that they seem to think they have free and unfettered access to. And, incidently, these are the same things that JEDEC is talking about incorporating into DDR-II." Now I see how this particular wingnut is screwed up. He thinks that having the write data valid window (tS + tH) be a large percentage of the cycle time is a good thing. Nothing could be more incorrect. This is going to be well beyond the understanding of the vast (unwashed) hordes who are likely to read this thread, but anyway... The write data valid time for a memory (or any kind of register) is the time that the design must hold the input valid. The longer that valid time, the more difficult it is for the engineers to hold it that long. The best write data valid time is the shortest one, not the longest one. This wingnut is saying that larger percentages are better. No design engineer would make that sort of mistake. The basic fact is that high speed interfaces are more difficult to engineer. This leads to higher expenses, more field failures, etc., etc., etc. The simple fact is that if RDRAM were an easy memory to hook to, a lot more guys would have designed it into their equipment. But right now, the DDR chipsets on design boards outnumber RDRAM chipsets by about 4 to 1. Part of that is cost, but another contribution is the ease of design associated with DDR. Why do you guys think that Altera and Xilinx support DDR (and have for several years) but neither support RDRAM, nor have any announced plans to do so? RDRAM is a pain in the ath to use. -- Carl

To: Dave B who wrote (48682)	8/2/2000 12:48:01 PM
From: gnuman	Respond to of 93625

Dave B. re: "Valid data" window. Unfortunately for me I can no longer find the source of my information and I didn't save it. (You and the thread can assume it never existed). <g> It was a worse case specification of system parameters for PC800. I did save a pdf file from HP, (which also no longer exists on the net), that shows waveforms from an RDRAM system, including the read/write data eye. I can e-mail it to you if you'd like. (A large pdf file). IMO, if the valid data for PC800 is 630ps in a system, three RIMM's should have been a piece of cake. Got tired of searching for the source, but if I find it in the future I'll post it on the thread. Since I can't post it now, I won't argue with your e-mail friend.