Silicon Investor (SI) -- The First Internet Community

STOCKTALK

We've detected that you're using an ad content blocking browser plug-in or feature. Ads provide a critical source of revenue to the continued operation of Silicon Investor. We ask that you disable ad blocking while on Silicon Investor in the best interests of our community. If you are not using an ad blocker but are still receiving this message, make sure your browser's tracking protection is set to the 'standard' level.

Technology Stocks : Rambus (RMBS) - Eagle or Penguin -- Ignore unavailable to you. Want to Upgrade?

To: richard surckla who wrote (48809)	8/2/2000 10:05:49 PM
From: jim kelley	Read Replies (1) \| Respond to of 93625

Hmmm.... I guess Bilow is not disciplined enough yet to design to a standard. Violations are more fun?

To: richard surckla who wrote (48809)	8/3/2000 11:43:05 PM
From: Bilow	Read Replies (1) \| Respond to of 93625

Hi richard surckla; Good that you guys are going back through my old posts! Bad for you that you haven't found much to complain about... Re " I believe that DDR SDRAM is at about the same stage of development as the Direct Rambus is." Back when I wrote this, #reply-9140140, it was April of 1999, and DDR and (direct) RDRAM were at roughly the same stage of development. Intel pushed RDRAM ahead later that year, but now DDR has caught up. Re "Amusing side note: The SSTL2 spec requires that the internal positive supply voltage of SSTL2 compliant parts be no greater than the I/O supply voltage. I am not sure why this requirement is there, and the DDR makers probably aren't either, as most of them violate it." #reply-9120282 This is so inconsequential as to be almost beyond belief. In any event, this provides a demonstration of my even-handed treatment of DDR and RDRAM. While what I wrote at that time was true, since then DDR has met the requirement. See, for instance: micron.com Note that in the above, Vdd = Vddq = 2.5V. The previous generation parts had Vdd = 3.3V, which was what I was commenting on back in April of last year. Re "So lack of a JEDEC standard doesn't slow down use of a memory by very much. It may seem complicated to someone who doesn't live and breath memory, but for engineers, this is not a big deal. (We use stuff like this to give lame excuses to management on why we are missing the schedule for a project. Shhh! :)" This was from #reply-9088373, (which you didn't give a convenient link to), and you neglected to include the preceding commentary, which was true then, and is still true now: DRAM designers have dealt with minor differences between vendor's specifications in new DRAM technologies for all the 15 years I have been designing high speed memory controllers. While the different DDR SDRAM makers do have different specifications, the differences are quite minor, and it is usually possible to design a single controller that will work with multiple part sources. This is not some new "problem" of DDR, but is a very minor part of memory design. An example of how this sort of thing was done with the issue of initializing SDRAM is well explained by this Micron pdf formatted primer: Achieve Maximum Compatibility in SDRAM/SGRAM Design (pdf) micron.com -- Carl