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Technology Stocks : Rambus (RMBS) - Eagle or Penguin -- Ignore unavailable to you. Want to Upgrade?

To: pheilman_ who wrote (48965)	8/5/2000 5:07:48 AM
From: NightOwl	Read Replies (1) \| Respond to of 93625

Why thank you Paul H. You EE guys who are still capable of credible independent thought really should do more posting. I have a ton of questions about this stuff as do others I am sure. And on behalf of Mom & Pop's everywhere, posting or just lurking, I can only say that if it weren't for you, Scumbria, Ali, GVT, Dan3, Gene P., Carl of course and a few others SI would be one sorry board. ...Now that I have offered my humble obeisance to the Lords of Excellon (:8), I have another question (which will sound like many questions to most of the M&P's around here, but I am sure you will recognize their singularity of purpose:8). Let me pose this series of true/false propositions: 1. DRDRAM and RDRAM are memory products optimized for the storage and accessing of Packetized data. 2. That the core designs and bus characteristics of these same products optimally service data Packets characterized by (a) a given size range whether measured by word length or number of bits, and (b) a highly predictable order of presentation into and out of the memory core. 3. Put another way for these products to function at the peak of their capabilities they must avoid applications in which the software being run, as well as the CPU and subsystems making calls on main memory require the writing and reading of data Packets which are either too short or too long in comparison to the DRDRAM's preferred Packet size; as well as applications which require a high degree of random access to particular data Packets rather than a highly predictable access order. 4. Everytime a DRDRAM gets a call for an undersized or oversized Packet, or one which is not located at the "predicted" memory address, the lower the level of bandwidth the chip is able to sustain in comparison to its peak bandwidth performance. 5. That both the size of the data Packets and their order of presentation to and selection from the memory core in the VAST majority of PC applications from servers to portables are determined by numerous variables from the nature of the software being run, the CPU and controller designs, the FSB design, the number of subsystems with access to memory and their respective bus designs or bridges to the main memory core. 6. Although for a given PC it would be a fairly simple matter to design a main memory benchmark which presented DRDRAM with its optimum Packet size and order, doing so would have the, ...unsavory to some... side effect of pinpointing the exact type of PC environment best suited to this design. 7. As a result of 1-5, the real world PC environments in which DRDRAM could approach its potential, justify its added costs, and be allowed to perform at its peak level on a sustained basis, are as scarce as Hen's teeth. Now my question is which of these propositions is true and which, if any, are false. :8) After we establish the parameters of this "Truth Table" we will move on to the nasty business of the market for WQRSL,... in Cincinnati. (Hee:8) 0\|0