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Technology Stocks : Advanced Micro Devices - Moderated (AMD) -- Ignore unavailable to you. Want to Upgrade?

To: dale_laroy who wrote (3964)	8/8/2000 11:50:21 AM
From: Joe NYC	Read Replies (2) \| Respond to of 275872

Dale, Unlike most previous processors, the Athlon does not support critical word first presentation of data, therefore the latency is the entire length of the burst, which is significantly impacted by doubling the data rate. I would guess an average of 15% for Athlon in a single processor system. Let me see if I understand this: Are you saying that on L1/l2 cache miss, when the system has to access data from RAM, the system waits for the full cache line to be filled (64 bytes?) before the processing can proceed? There was some discussion about it here, but I don't think anybody had a definite answer. Anyway, this means 8 memory cycle, or 7 memory cycle delay after the critical word has been read? If it's true, it stinks. 7 memory cycles can mean 70 CPU cycles with PC-100 and 1 GHz CPU. DDR will cut this delay in half to 3.5 cycles. I think it should have significant impact on performance. BTW, this (not sending the critical word to the CPU) seems to be the CPU issue, so it can't be "fixed". The only thing that can be done is to lessen the impact by DDR. A 2 channel DDR chipset would improve the performance further. How much performance do you think is lost because of this vs. Piii? Joe

To: dale_laroy who wrote (3964)	8/8/2000 8:02:22 PM
From: Dan3	Respond to of 275872

Re: I would guess an average of 15% for Athlon in a single processor system. That's great to hear, and has more behind it than my WAG. Regards, Dan

To: dale_laroy who wrote (3964)	8/9/2000 6:59:42 AM
From: Hans de Vries	Read Replies (1) \| Respond to of 275872

Dale. It's hard to believe that the Athlon doesn't use the critical word first. The 8 cycle latency from L1 miss to L2 data is most likely the result of keeping the whole bus/cache interface unmodified for the Thunderbird. This bus interface can handle clock-multipliers for L2 cache and therefor probably needs 2 registers between Processor and L2 cache both ways (Address out / Data in) This would explain 4 of the 8 cycles. The remaining 4 would then be the real L2 access time (L2 Tags, then L2 Ram) Probably the only thing which is modified in the Athlon Core is the L1 dirty bit which makes the L1 work as an Exclusive Cache when it is stuck to "1". BTW. Good to see you on this thread! (see also amd.com Regards, Hans