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To: Paul Engel who wrote (4496)8/11/2000 1:13:36 AM
From: kash johalRead Replies (2) | Respond to of 275872
 
Paul,

Re: Tualitin

Probably will be a kick ass chip.

Its probably pin limited - no wonder they doubled the l2 cache.

Do you have a die size estimate at 0.13.

Timing for mid 2001 seems long.

What is earliest you see it introduced - is Q1 2001 feasible.

regards,

Kash



To: Paul Engel who wrote (4496)8/11/2000 10:38:02 AM
From: CirruslvrRespond to of 275872
 
Paul - RE: "That schedule gives Intel a LONG TIME to debug and optimize Tualatin !"

Do you think Intel will have any new PIII between the current C0 stepping and Tualatin?

Edit - never mind, you already answered Joe about this.