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To: semiconeng who wrote (107574)	8/15/2000 8:59:55 AM
From: Dan3	Read Replies (1) \| Respond to of 186894

Re: 50 Die From Edge loss? HA HA HA HA Think again - try calculating how many 10 x 10 (approx) squares intersect the perimeter of a 200mm diameter circle. Or is a PIII missing only one little corner just as good as a whole one? it was 15.4 million from 1 Fab in Q2 After production started showing up from the C0 shrink - I couldn't recall the new dimensions (90 something mm as nearly as I can recall) which means that the number of possible die was actually quite a bit higher - yields may even be lower than I calculated! Did Intel drop below 50% yields on the C0 stepping? :-) Dan

To: semiconeng who wrote (107574)	8/15/2000 9:10:25 AM
From: Scumbria	Read Replies (1) \| Respond to of 186894

Semicon, Are you Yousef? Scumbria

To: semiconeng who wrote (107574)	8/16/2000 12:31:30 AM
From: Petz	Read Replies (2) \| Respond to of 186894

semiconeng, Dan's estimate of 20% waste space is not far from correct. For a 12mm by 10mm die, the absolute minimum waste space, if there is ZERO spacing between die it is possible to squeeze 236 die on the wafer, for a waste % of 9.9%. If there's just a border of 0.2mm between each die, you can only fit 226 die, for a waste % of 13.7%. With 0.5 mm between die, you can fit 213 so wasted space is 18.6%. There may be additional wasted space around the edges of a wafer which I did not take into account. I made up a little spreadsheet to do this calculation, it was fun. Petz