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To: Dan3 who wrote (107623)8/16/2000 9:40:04 AM
From: semiconeng  Read Replies (2) | Respond to of 186894
 
Semiconeng,

John was speaking of the spacing between die, not edge loss - which you totally missed.

By the way, the lowered edge loss estimate makes Intel's yields look that much worse....

Dan


And I guess you missed that he was also basing his "assumption" on a 120mm^2 die size, which is far above the 90mm^2 die size of current CuMine, and therefore skewing all his other numbers. Nice tunnel vision Dan.

SemiconEng