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To: EricRR who wrote (107705)8/18/2000 1:30:29 PM
From: John Hull  Respond to of 186894
 
Ratbert,

pretty standard practice to bring up first silicon of new architecture on an N-1 process. Reduces the set of variables you have to deal with. Once you're happy with the silicon functionality, you move fast to cutting edge process.

only when you are forced do you try to do both at once - usually has high risk (remember K5 and early K6?).

regards,
jh



To: EricRR who wrote (107705)8/18/2000 2:05:33 PM
From: semiconeng  Respond to of 186894
 
Isn't Intel using only .25 for the Itanium? If true, why don't they use their best process for their premium system?

Also, I bet Intel doesn't release Itanium until it can at least get the MHz above the fastest Celeron at the time.


I know that Merced was "started up" on 0.25u, so I have no idea when those chips that were demo'd were made. As far as what process it's currently being made on, I'm not at liberty to say.

:-)

SemiconEng



To: EricRR who wrote (107705)8/18/2000 2:55:38 PM
From: Jim McMannis  Respond to of 186894
 
RE:"Also, I bet Intel doesn't release Itanium until it can at least get the MHz above the fastest Celeron at the time."

So you are basically betting the Itanium will never be released? <G>
Seems to me that the Itanium core was developed back when Mhz wasn't such a major concern of the chip world.

I'd really like to know why the Itanium hasn't been released yet. It's not like they have a bunch of IA-64 platforms to compete against. Something could be wrong...very wrong....

Jim