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To: Don Green who wrote (50339)	8/19/2000 12:55:30 AM
From: Don Green	Respond to of 93625

NEC, Toshiba retooling fabs for denser memories at 0.18 micron -- Process push under way for 256-Mbit DRAM Aug. 18, 2000 (Electronic Engineering Times - CMP via COMTEX) -- TOKYO - NEC Corp. and Toshi-ba Corp. have started retooling their DRAM fabs to produce devices with 0.18-micron line widths in preparation for volume production of 256-Mbit memory chips. But while the two companies are taking a similar approach to process technology for high-end devices, their product mix strategies are markedly different. Toshiba, attempting to get an early start on high-density devices and steer clear of competition for more mainstream parts, has opted to wind down production of 128-Mbit synchronous DRAMs in favor of Rambus and 256-Mbit devices as it keeps a lid on new DRAM wafer starts. NEC, which is also preparing to bring 256-Mbit chips on stream this year, is set to double its 128-Mbit SDRAM production capacity and increase wafer output while reducing 64-Mbit SDRAM production. NEC in recent months began shifting to 0.18-micron process rules starting with its 288-Mbit Rambus DRAMs, which the company is betting will penetrate high-end servers and workstations and then trickle down to desktop systems. The parts have shown early signs of improved yields over 64-Mbit and 128-Mbit-generation Rambus parts, which thus far have largely failed to become mainstream devices because of their high production cost and some DRAM vendors' refusal to make production commitments. After getting the 0.18-micron ball rolling, NEC intends to migrate quickly to narrower line widths. The company is shooting for introduction of 0.15-micron process rules by the end of the year, followed by 0.13 micron in April. NEC believes its introduction of its 0.13-micron process for system-on-chip devices earlier this year will give it a head start. "We're kind of jumping past 0.18 micron for logic," said an NEC spokesman here. The company's 0.13-micron process could serve as the basis for a unified DRAM process to be adopted by NEC and Hitachi Ltd., which have agreed to merge their DRAM operations in January. The two companies will jointly market and sell DRAMs produced by NEC's Hiroshima fab and Hitachi's Singapore fab, and they plan to adopt a single 0.13-micron process for production of 256- and 512-Mbit DRAMs, the NEC spokesman said. Recently, domestic and international executives from both companies met here to hammer out the details of the new company, including the name. In the meantime, NEC is stepping up its DRAM investment. It bumped up capital spending this year at its Hiroshima fab, increasing DRAM wafer output at the plant from 25,000 to 35,000 wafers per month. Its Shanghai fab is approaching full capacity, of 20,000 wafers per month, and has been granted approval to move soon from 0.35-micron to 0.25-micron design rules, the spokesman said. The new process rules and additional wafer starts will boost NEC's total DRAM production output from 20 million 64-Mbit-equivalent devices to more than 26 million by March. Most of the new capacity will be allocated for 128-Mbit SDRAMs, which will jump from 6 million units per month last May to 12.5 million next March. After a peak of 10 million units last March, output of 64-Mbit DRAMs will fall to 5 million by December and then to 1.5 million next March. NEC's production of 128-Mbit Rambus DRAMs will remain at 1 million per month for the rest of the fiscal year; 288-Mbit Rambus production will hit 750,000 units in December and rise to 1.25 million by March. Toshiba, for its part, will start shifting this year from 0.2-micron process technology to 0.175-micron design rules at its Yokkaichi factory in Japan. The company will also transfer the technology this fall to Taiwanese foundry partner Winbond Electronics Corp. Toshiba has agreed to transfer production technology to Winbond down to 0.13-micron design rules. The company monthly produces 21 million 64-Mbit-equivalent DRAMs now and expects total output to rise to 23 million units per month by December as it brings up the new process and emphasizes 256-Mbit production. Production of 128-Mbit SDRAMs is slated to fall from 6.5 million units this September to 5 million units by year's end. Also by the end of the year, Toshiba plans to produce 1 million SDRAMs and 500, 000 Rambus DRAMs at the 256-Mbit density. Toshiba, which is providing 128-Mbit Rambus DRAMs for Sony's Playstation 2, will churn out 3 million of those devices by the same period. Though the switch to 0.175-micron process will increase the number of chips per wafer, a Toshiba spokesman dismissed as groundless speculation local press reports suggesting it will lead to a huge jump in new capacity. Toshiba has no intention to boost the number of DRAM wafer starts, preferring instead to allocate more wafers to its NAND flash memory. These non-volatile memory devices, which are used for data storage in digital cameras and MP3 players, are in high demand, and Toshiba is one of the few suppliers making them. Samsung Electronics is the other major supplier. The Toshiba spokesman said that "[DRAM] wafer starts will remain the same, or maybe will be reduced as we employ a finer process. We would like to allocate more wafers to NAND flash rather than DRAM." He added that if Toshiba decides to increase DRAM wafer capacity, it will negotiate with partner Winbond to take on more production. So far, no such negotiations have taken place. eetimes.com -0- By: Anthony Cataldo Copyright (c) 2000 CMP Media Inc.