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Technology Stocks : Advanced Micro Devices - Moderated (AMD) -- Ignore unavailable to you. Want to Upgrade?

To: Bilow who wrote (5761)	8/20/2000 11:39:51 AM
From: Scumbria	Read Replies (1) \| Respond to of 275872

Carl, For performance reasons, every L1 cache access requires that an entire line be read out of each way, and prepared for muxing back to the execution units. This is typically (32 or 64) bytes X (4 or 2) ways X 8 bits/byte X 3 accesses (one I cache and 2 dcache). That is 3Kbytes read out into latches on each cycle. Besides the power required to fire up the data arrays, and the large power consumption required to run 4 high speed 20 bit compares on the tags, the data reads and muxing consume a substantial amount of power. This is one reason why any implementation of a high performance x86 processor (including Transmeta) is prone to consume a substantial amount of power. RISC processors can do better, because they keep operands in the register file, which consumes considerably less power than the L1 cache. Transmeta is putting very large caches onboard, to reduce DRAM accesses (and thus power consumption.) They also are using low power DDR DRAM modules. (But I guess you knew that ;^)) Scumbria