To: NightOwl who wrote (50475 ) 8/21/2000 1:27:55 AM From: Bilow Read Replies (1) | Respond to of 93625 Hi NightOwl; Re RDRAM in communication. You are probably referring to this passage:By this rule of thumb, a full-duplex OC-192 processor should sustain at least 5 Gbytes/s (40 Gbits/s) to DRAM. Because double-data-rate SDRAM is less efficient than standard SDRAM, even a 256-bit-wide DDR memory at 266 MHz would not reach this level. Not only would such a wide interface require more than 500 pins, it would be difficult to support less than 256 Mbits using standard dual in-line memory modules. Thus, most OC-192 processors are likely to move to Rambus. Four 800-MHz RDRAM channels can sustain 5 Gbytes/s using only about 200 pins, making it possible to use as little as 64 Mbits of memory. Other emerging DRAM technologies, such as FCRAM, may also be used. In this regard, Vitesse is ahead of the game by integrating an RDRAM controller on its IQ2000. Most other devices are using PC100 SDRAM to reduce cost, while IBM's Rainier net processor supports 200-MHz DDR SDRAM. These other vendors will have to spend more design time integrating RDRAM in their future devices, although IBM appears willing to accept the larger pin counts required by SDRAM. eetimes.com This reads like a bad rewrite of a Rambus / Vitesse press release, and probably is. Hey,Linley Gwennap has to get her stuff from somebody! (Wait till you read what Vitesse has to say when they come up with a network processor that uses DDR. It'll be the same sort of crap.) For a network processor, you want a relatively small memory, so the systems to compare to are the graphics processor memories, not regular desktop memories, and the graphics guys are all solidly DDR now. Bandwidths of 5GB/sec aren't a big deal for Nvidia, who includes them in (relative to network processors) cheap graphics cards. The latest Nvidia card is shipping with 6.4GB/sec memory interface, and that is only 128 bits wide. Already point 2 point DDR memory chips are being sampled which give an 8GB/sec bandwidth when used x128. The suggestion that efficiency of DDR is significantly below that of SDRAM is not correct, particularly with regard to packet processing. Maximum efficiency packets are what, 1500 bytes long? With a 16-byte wide memory interface, passing 16 bytes twice each clock, that means that you are going to end up with bursts about 45 clocks long, at least for the most efficient network usage. Losing a clock isn't going to lose you much more than 10% as long as memory is stored in DDR at least 256 bytes long. If that doesn't work, then split the DDR into two 64-bit wide interfaces, and now you're down to 128 bytes for the same 10% bus inefficiency. (And that is worst case bus inefficiency.) In short, DDR is perfectly suited for network processing. There is another issue, and that is the fact that memory bandwidths for network processing is increasing faster than the need for memory size. That means that embedded is probably the next stage, not RDRAM nor DDR:Once touted for use with graphics accelerators, embedded DRAM appears to be making a comeback in communications. But unlike graphics, where many chip makers tried unsuccessfully to embed DRAM themselves, the networking field is seeing startups emerge that specialize in embedded DRAM. ... One of them, Dmel Inc. , will begin offering its embedded DRAM cores commercially, primarily to the ASIC designers who work with Taiwan Semiconductor Manufacturing Co. Ltd. ... Startup EZchip Technologies Ltd. is loading its processor with embedded DRAM, and fellow startup Silicon Access Networks actually began life as an embedded DRAM provider. eetimes.com Looking for faster packet speeds, MMC Networks Inc. is using embedded DRAM cells in its latest network processor. eetimes.com Pressured by a need to boost I/O bandwidth and keep chip die sizes in check, some Ethernet controller vendors are turning to embedded DRAM as an on-chip buffer memory. ... Both Level One and Mosaid talked about their plans at the recent Symposium on VLSI Technology here. ... It will be the second networking chip the company has designed using embedded DRAM, the first being a switching device for Newbridge Networks, said Richard Foss, chairman of Mosaid. ebnews.com TAEC introduced three families of application-specific cores earlier this year. For bandwidth-dependent applications, such as networking, video, or graphics, the company has designed high-bandwidth cores that feature 48-ns access times with more than 6.4-Gbyte/s bandwidth using a 256-bit-wide data bus.ebnonline.com Infineon Technologies Announces 0.18 micron Embedded DRAM Process The C10DE state-of-the-art process technology is the next step in Infineon 's strategy to offer system level integration (SLI) ASICs for networking and telecom systems (switches, routers and base stations), digital consumer products (3G mobile phones and PDAs), and computer peripherals (DVD drives and printers) among others. au.us.biz.yahoo.com -- Carl