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To: Cirruslvr who wrote (5811)	8/21/2000 2:19:14 AM
From: Charles R	Read Replies (1) \| Respond to of 275872

<What's your defense for Intel not offering SMP with Willy?> Anyone who expects any serious SMP configuration based on a multi-drop bus running faster than 100 or 13MHz has no understanding of busses. AMD has proved that even with point-to-point architecture and source synchronous clocking these wide busses are a major pain. Choking the FSB of Willamette to make SMP systems would probably result in a performance hit that makes such an effort meaningless. (Scumbria, Kap any guesses on what the performance penalty would be if the FSB is throttled down to 100MHz?) It will be very interesting to see what kind of problems Intel will have with quad pumped bus for Wilamette - even for single processor configurations.

To: Cirruslvr who wrote (5811)	8/21/2000 3:00:18 AM
From: Scumbria	Respond to of 275872

Cirrus, Its L1 data cache is 8 Kilobytes Are you sure about this? The performance will be terrible if it is true. Scumbria