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Technology Stocks : Advanced Micro Devices - Moderated (AMD) -- Ignore unavailable to you. Want to Upgrade?

To: minnow68 who wrote (5829)	8/21/2000 10:32:59 AM
From: Scumbria	Read Replies (2) \| Respond to of 275872

Mike, Your analysis is ignoring the fact that cache accesses are pipelined. Despite having a 3-cycle absolute latency, the effective latency of the Athlon L1 cache is close to zero, because it is being accessed almost every cycle. The only time when L1 cache latency becomes an issue is when bubbles appear in the load queue. This can occur because of branch misprediction, or because of poor scheduling by the compiler. The small fast L1 data cache on Willy will be a disaster for two reasons. 1. The hit rate is low. 2. It will limit the maximum clock frequency. Do you remember how thrilled I was 2 years ago when I heard that AMD had increased the latency of the K7 cache to 3 clocks? This was because they had broken the psychological barrier of a brain-dead short pipeline mentality. The Willy team seems to have made two fundamental mistakes. 1. The small fast L1. 2. The double speed ALU. The Willy team is our friend! Scumbria