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To: mishedlo who wrote (50569)	8/21/2000 2:05:00 PM
From: NightOwl	Read Replies (1) \| Respond to of 93625

Thanks mishedlo, Sorry if the error wasn't obvious to all. If you read the article, ...numbers and all, I assume you noted that they reported a latency on their DRDRAM subsystem of 60 nanoseconds for any random access of the first word from the cache line. And that the remainder of the random access LATENCY was accounted for by an additional 30 nanoseconds to get the rest of the cache line off the chip. Now I have no idea what OS and program they are going to use to crunch their numbers, but it is patently obvious that the software is NOT going to be pumping streaming packets of pixels to and from the CPUs. Considering the whopping number of LATENCY laden DRDRAM chips in this paralelloputer they are going to have substantial latency penalties that will reduce its effective bandwidth efficiency. So the question remains: What do you consider High Latency? [To Scumbria: Which isn't to cast any aspersions at LANL. Obviously this design win was obtained without any hands on testing of the final product which is yet to be built. Moreover, if they're only going to run these problems as often as they once did the nuclear tests themselves, no doubt the latency delays they suffer, and thus the sustained bandwidth the system maintains is of relatively little import. Besides, it is government work.:8] 0\|0