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Technology Stocks : Intel Corporation (INTC) -- Ignore unavailable to you. Want to Upgrade?

To: Scumbria who wrote (107924)	8/21/2000 7:15:41 PM
From: EricRR	Read Replies (3) \| Respond to of 186894

As I posted on the other thread, Sharky reports that Willy's branch prediction is 30% better than P3. If true, what does this mean for IPC? 70% x2 pipeline size comes out to 140% percent branch penalty. 1.4GHz divided by 1.4 is the performance of a 1GHz Pentium 3.

To: Scumbria who wrote (107924)	8/22/2000 3:31:24 PM
From: pgerassi	Respond to of 186894

Dear Scumbria: Re: P4 Instruction and data caches What I find very interesting (and weird) is that P4 has an 8K Data Cache but a 12,000 micro ops instruction cache. If the underlying engine is a 32 bit RISC, 12,000 micro ops works out to (at least) 48K Instruction Cache. In all of the processors that do high performance computing, the data cache is as large or larger than the instruction cache (if not combined together). Either someone is wrong about the sizes (if off by a decimal point, 1,200 RISC instructions * 1.5 words per instruction * ~4 bytes per instruction yields ~ 8K), or Intel needs this large a trace cache to even get the IPC up enough to not be totally rediculous. This may be why the die size is up to 170% as large even with less pipe width. All in all, an unusual condition for Intel to be in. I can not wait to see what the true real world IPC and CPU speeds are. I wonder if, Intel would be better off to go the CMP route as well, with twin P3s plus northbridge on a chip, than this overlong pipeline CPU. Pete