Silicon Investor (SI) -- The First Internet Community

STOCKTALK

We've detected that you're using an ad content blocking browser plug-in or feature. Ads provide a critical source of revenue to the continued operation of Silicon Investor. We ask that you disable ad blocking while on Silicon Investor in the best interests of our community. If you are not using an ad blocker but are still receiving this message, make sure your browser's tracking protection is set to the 'standard' level.

Technology Stocks : Intel Corporation (INTC) -- Ignore unavailable to you. Want to Upgrade?

To: Tenchusatsu who wrote (107938)	8/21/2000 8:34:40 PM
From: kapkan4u	Respond to of 186894

<<I think that it was you who said that P4 retained the clunky PIII decoders running at half the speed (700MHz for the 1.4GHz part) of the core.> You must be mistaken. I never said that.> You did say that some parts of P4 run at half the core frequency. Hans DeVries said that P4 kept the PIII decoders running at half speed. It all adds up. <So what? That's no different from a regular instruction cache.> Half speed L2/decoders in P4 is the reason why there is a big difference from L1 I-cache. The difference is latency. Kap