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To: Don Green who wrote (50769)	8/22/2000 3:57:41 PM
From: Don Green	Read Replies (1) \| Respond to of 93625

Intel Unveils Technical Details of P4 Architecture Aug 22, 2000 --- At the Intel Developer Forum in San Jose today, Intel officially announced details of the Pentium 4 processor. This week, Intel will unveil technical details of its NetBurst architecture, the next-generation internal processor design behind the Pentium 4 chip. NetBurst is Intel’s first new core design since the P6 architecture first seen in the Pentium Pro processor in 1994. The Pentium 4 will have 42 million transistors. The Pentium III has only 28 million. It will feature a front-side bus that operates at 400MHz, three times the speed of the Pentium IIIs, which will enable data transfer of 3.2Gbyte/sec. The P4 uses the controversial Rambus DRAM (RDRAM). As revealed recently by Electronic News, Intel’s confidential Desktop 2001 roadmap specifies that by 2002, RDRAM will be relegated to high-end P4s with mainstream models using an undefined SDRAM memory (probably PC-133 or double data rate. The NetBurst microarchitecture features greater efficiency by paradoxically requiring extra steps in the execution of instructions. NetBurst requires 20 steps to execute an instruction, twice as many as in the P6 core. This allows designers to simplify the chip’s circuitry that makes it possible to run the chip at higher frequencies. Intel has included a new rapid execution engine allowing some instructions such as basic arithmetic operations like addition and subtraction to be performed separately, the new engine operating at twice the frequency of the rest of the chip. Intel also claims the NetBurst architecture can operate six instructions at once on a sustained basis. Efficiency is improved within the chip by its shuffling the order in which instructions are processed. The Pentium 4 will debut in the fall at a speed of at least 1.4GHz.