Silicon Investor (SI) -- The First Internet Community

STOCKTALK

We've detected that you're using an ad content blocking browser plug-in or feature. Ads provide a critical source of revenue to the continued operation of Silicon Investor. We ask that you disable ad blocking while on Silicon Investor in the best interests of our community. If you are not using an ad blocker but are still receiving this message, make sure your browser's tracking protection is set to the 'standard' level.

Politics : Formerly About Advanced Micro Devices -- Ignore unavailable to you. Want to Upgrade?

To: Cirruslvr who wrote (122928)	8/23/2000 10:38:42 AM
From: Ali Chen	Read Replies (1) \| Respond to of 1578930

<what this split transaction bus design for Willy is in laymans terms?> It must be nothing principally new relative to P-II and Pentium-Pro 1996 bus. It means that the transaction on the bus is split into five phases - request, error, snoop, response, and data. Each phase runs on a separate group of signals allowing to pipeline the phases. In case of _several_ active bus agents (say, CPU, AGP in DME mode, UDMA) it allows for better bus utilization (given relatively sluggish memory latencies in modern PC). I guess they just added something like AGP4 quadrupling data transfer protocol to the old bus. Regards, - Ali