To: Dave B who wrote (50944 ) 8/23/2000 4:48:14 PM From: Scumbria Respond to Dave,The number of internal banks a DRAM has is perhaps the biggest factor in determining actual system latency. This is because of the fact that a DRAM can access data much faster if it is located in a bank that has been activated. By activated, we really mean that the data is located in a bank that has been pre-charged. The pre-charged bank can either be the same page (row) that is currently being accessed, or it can be in a bank that is not currently being accessed. If the data is located in a pre-charged bank, we often call this a page hit, meaning the data can be accessed very quickly without a delay penalty of having to close the current page and pre-charge another bank. On the other hand, if the data is in a bank that has not been pre-charged, or in a different row within the bank currently being accessed, a page miss occurs and performance is degraded due to the additional latency of having to pre-charge a bank. The memory controller designer can minimize latency by keeping all unused banks pre-charged. Therefore, more internal DRAM banks increases the probability that the next data accessed will be to an active bank and minimizes latency. The memory controller designer can minimize latency by keeping all unused banks pre-charged.
