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Technology Stocks : Intel Corporation (INTC) -- Ignore unavailable to you. Want to Upgrade?

To: EricRR who wrote (108245)	8/24/2000 8:49:23 PM
From: Tenchusatsu	Read Replies (1) \| Respond to of 186894

EricRR, <is "prefetch" misprediction the same as a general "branch" misprediction penalty?> In this context, I believe so. The article was talking about prefetched instructions, not prefetched data like that enabled by SSE and SSE2. And of course, to prefetch instructions to a reasonable depth for a long pipeline, you have to accurately predict the branch instructions that show up. <Is the above quote just "spin" on the idea that the branch mispredict for code in the trace cache will only be 20 clocks, vs 26 for code outside the trace? (BTW are those numbers right?)?) Did you say yesterday that P3 has a 13 clock mispredict penalty? Or was that total pipe size?> I don't know if any of those numbers are right. But I do know that Pentium III (and all the P6 cores before it) has a 12 to 14 stage pipeline. <Sounds to me like Intel is setting themselves up for more polymorphic code problems, which by their nature have high mispredict rates.> I didn't know there was a lot of polymorphic assembly code out there. But I do know that Pentium 4's branch prediction unit is better than Pentium III's. (Then again, with such a long pipeline, it better be.) Tenchusatsu