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Technology Stocks : Intel Corporation (INTC) -- Ignore unavailable to you. Want to Upgrade?

To: Dan3 who wrote (108447)	8/26/2000 11:36:39 AM
From: Elmer	Read Replies (1) \| Respond to of 186894

Re: "On large cache (server) CPUs, Mustang/Athlon will be smaller than Xeon/P3!" You may be right but with AMD's difficulty producing K7s in volume they are going to have one heck of a time producing those large dice, even with the benefit of LI. If they can't make K7s in volume how are they going to make Mustangs? EP

To: Dan3 who wrote (108447)	8/26/2000 11:52:39 AM
From: semiconeng	Read Replies (1) \| Respond to of 186894

Too bad INTC can't handle local interconnect: They didn't want it. You seem to be under the impression that local interconnect is a great thing. Actually, it's a real pain in the butt, yield-wise, as AMD found out with K63: http://www.eetimes.com/story/eezine/OEG19990312S0012 The local interconnect continues to be a two-edged sword. On the one hand, this layer of poly or metal underneath metal-1 can substantially improve the size of some standard cells. For instance, Gwennap estimated that AMD's use of local interconnect in the K6-III's on-chip L2 cache makes its SRAM so small that the 0.25-micron K6-III die is likely to be smaller than the as yet unannounced Intel Pentium-III "Coppermine" die, which has the same amount of cache but in a 0.18-micron process. But the local interconnect is also a major pain for process engineers. "Intel has told me that they evaluated local interconnect for their P856.5 process, and decided it wasn't worth the problems," Gwennap said. And that seems to be exactly the problem Motorola was having as recently as Nov 99: http://www.chipworks.com/News/11Motorola%20Copper.htm According to Ms. Elvidge, "the Motorola copper device is an 8M-bit synchronous static RAM organized as 256K words by 36 bits. It is manufactured in 0.15µm CMOS technology and incorporates four copper interconnect layers, a tungsten local interconnect layer, and one polysilicon layer. The CMOS 6-T memory cell is comprised of four n-channel and two p-channel transistors with shallow trench isolation (STI "What makes this chip so important is that it is the first copper memory chip available to the commercial market" stated Ms. Elvidge. Motorola is currently producing only two parts in copper, the 8M SRAM memory device and more recently the Power PC G4 processor. Motorola is presently experiencing difficulty shipping the required volumes of the new Power PC G4 for Apple Computers, which is likely attributed to problems with the copper process" said Ms. Elvidge. SemiconEng

To: Dan3 who wrote (108447)	8/26/2000 2:56:06 PM
From: Paul Engel	Read Replies (2) \| Respond to of 186894

Lewinsky-Dan - Re: "Too bad INTC can't handle local interconnect:" Yep - Intel made a trade off with LI. But why do you jet your jollies off by gloating over Motorola ? And that's why Intel is the LEADER in profits and Profit Margins - by going for HIGHER YIELDS instead of smaller die. Too bad for AMD that Intel has surpassed AMD !!! The ThumperTurd is 120 sq. mm WITh LI and 256K L2 cache/128K L1 cache - while Intel's Pentium III is 90 sq, mm with the SAME L2 cache and 32K L1 cache. And the Pentium III is faster in GHz as well as FASTER at equivalent clock speeds. Believe it, Mr. Blow Hard !