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To: Scumbria who wrote (6861)8/29/2000 1:26:55 AM
From: THE WATSONYOUTHRead Replies (1) | Respond to of 275872
 
Dual Vt methodologies usually place high Vt cells only along non-critical paths. Chances are that the critical path in question already has low Vt cells, and will not
lend itself to easy improvement.


Yes, but I believe (based on the large power increase) that this process may now have some paths that contain devices with too low Vt for proper operation. There can be significant channel length variations across the chip(many causes) which only become critical and apparent at the extreme edge of the process window.

just speculating
THE WATSONYOUTH